On Thu, Jan 26, 2017 at 09:25:44AM +0100, Daniel Schultz wrote: > This patch is based on a patch from the U-Boot and fixes two errors with > the LCDC. Original commit message from Jyri Sarha [1]: > "Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, > and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With > the default values LCDC suffers from DMA FIFO underflows and frame > synchronization lost errors. The initialization values are the highest > that work flawlessly when heavy memory load is generated by CPU. 32bpp > colors were used in the test. On BBB the video mode used 110MHz pixel > clock. The mode supported by the panel of am335x-evm uses 30MHz pixel > clock." > > The register values are generated by testing, because there is no formula > to calculate them. Also from Jyri Sarha [1]: > "In practice the only rule to find an optimal value is to find as high as > possible REG_PR_OLD_COUNT value that does not produce LCDC FIFO > underflows under worst case scenario. The worst case happens when the > highest pixel clock videomode with maximum bpp is used while memory > subsystem is stressed by endless stream of writes hitting the same > memory memory bank (can be the same address)." > > It only contains the BeagleBone Black and the Phytec SoM, because I > don't have other boards. > > [1] https://patchwork.ozlabs.org/patch/704013/ > > Signed-off-by: Daniel Schultz <d.schultz@xxxxxxxxx> Applied, thanks. Nice fix, I think I have been searching for this for a while some time ago without success. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
