Hi everyone,
I'm using BareBox and xload 2016.11.0 with custom BSP patches for my
Altera Cyclone V SoCFPGA based custom board, which boots from QSPI.
The board boots fine, but I ran into a weird boot timing issue when
playing around with the LOGLEVEL configuration options in xload. Before
playing around with them, my initial LOGLEVEL options were as follows:
CONFIG_COMPILE_LOGLEVEL=6
CONFIG_DEFAULT_LOGLEVEL=7
I ran into the boot timing issue when setting them as follows:
CONFIG_COMPILE_LOGLEVEL=6
CONFIG_DEFAULT_LOGLEVEL=5
The symptoms were that xload reported the following errors:
mtd0: failed to get image size
mtd0: failed to detect barebox and it's image size so use 1048576
It then went on to load and boot the barebox image successfully.
To debug the problem, I hex-dumped the barebox image header to the
terminal after it had been read by read_image_head() in
"lib/bootstrap/devfs.c" and found it to contain only '\xFF' bytes.
However, if I insert a small delay by calling mdelay(1) before reading
the barebox image header, it is read correctly and I don't get the error
messages.
It seems like a small delay is required after the Cadence QSPI driver
("drivers/mtd/spi-nor/cadence_quadspi.c") has set up the flash chip
before it is in a useable state. Adding a call mdelay(1) just before
cqspi_probe() returns fixes the problem for me, but I'm not sure if
that's the best way to fix it!
For reference, my flash chip is a Spansion s25fl256s1 (32768 Kbytes) and
the Cadence QSPI controller built in to the SoCFPGA is being clocked at
400 MHz.
--
-=( Ian Abbott @ MEV Ltd. E-mail: <abbotti@xxxxxxxxx> )=-
-=( Web: http://www.mev.co.uk/ )=-
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