On Tue, Oct 04, 2016 at 06:34:45AM -0700, Andrey Smirnov wrote:
> On Mon, Oct 3, 2016 at 11:32 PM, Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> wrote:
> >> +static int vf610_twr_sdhc1_clock_init(void)
> >> +{
> >> + int err;
> >> + struct clk *esdhc1_div, *esdhc1_div_parent;
> >> +
> >> + if (!of_machine_is_compatible("fsl,vf610-twr"))
> >> + return 0;
> >> +
> >> + esdhc1_div = clk_lookup("esdhc1_div");
> >> +
> >> + if (IS_ERR(esdhc1_div))
> >> + return PTR_ERR(esdhc1_div);
> >> +
> >> + esdhc1_div_parent = clk_get_parent(esdhc1_div);
> >> + if (IS_ERR(esdhc1_div_parent))
> >> + return PTR_ERR(esdhc1_div_parent);
> >> +
> >> + err = clk_set_rate(esdhc1_div,
> >> + clk_get_rate(esdhc1_div_parent));
> >> + if (err)
> >> + return err;
> >> +
> >> + clk_put(esdhc1_div);
> >> +
> >> + return 0;
> >> +}
> >> +coredevice_initcall(vf610_twr_sdhc1_clock_init);
> >
> > What's the background for this? Should it be made SoC specific?
>
> The divider that peripheral bus clock is connected to before that
> clock goes to SDHC controller is not set to one, so if this is not set
> the parent clock ends up being something around 12Mhz.
This sounds like this should be done in the CCM init code as part of the
"bring the clocks to sane defaults", possibly for the other SDHC
controllers aswell.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@xxxxxxxxxxxxxxxxxxx
http://lists.infradead.org/mailman/listinfo/barebox
