The NoC regulator only passes the QoS signals through if it is
in bypass mode. This is a safe setting to give the IPU priority
over other requests. The kernel may change it to some other setting
once it knows the bandwidth requirements of the use-case.
Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
---
arch/arm/mach-imx/imx6.c | 11 +++++++++++
arch/arm/mach-imx/include/mach/imx6-regs.h | 3 +++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 567559033770..f90eec8bd2c8 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -97,6 +97,7 @@ void imx6_init_lowlevel(void)
void imx6_setup_ipu_qos(void)
{
void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
+ void __iomem *fast2 = (void *)MX6_FAST2_BASE_ADDR;
uint32_t val;
if (!cpu_mx6_is_mx6q() && !cpu_mx6_is_mx6d() &&
@@ -119,6 +120,16 @@ void imx6_setup_ipu_qos(void)
val &= ~(IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK);
val |= (0xf << 16) | (0x7 << 20);
writel(val, iomux + IOMUXC_GPR7);
+
+ /*
+ * On i.MX6 QP/DP the NoC regulator for the IPU ports needs to be in
+ * bypass mode for the above settings to take effect.
+ */
+ if ((cpu_mx6_is_mx6q() || cpu_mx6_is_mx6d()) &&
+ imx_silicon_revision() >= IMX_CHIP_REV_2_0) {
+ writel(0x2, fast2 + 0xb048c);
+ writel(0x2, fast2 + 0xb050c);
+ }
}
int imx6_init(void)
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index 68be43c9ab5b..e661c4ed120b 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -3,6 +3,9 @@
#define MX6_GPMI_BASE_ADDR 0x00112000
+#define MX6_FAST1_BASE_ADDR 0x00c00000
+#define MX6_FAST2_BASE_ADDR 0x00b00000
+
#define MX6_AIPS1_ARB_BASE_ADDR 0x02000000
#define MX6_AIPS2_ARB_BASE_ADDR 0x02100000
--
2.8.1
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