Hi Sascha. On Tue, Sep 13, 2016 at 04:08:09PM +0200, Sascha Hauer wrote: > Enable parent rate propagation for clk_gate2 to allow the > clock consumers to adjust their rates. > One effect of this is that the i.MX6 NAND controller now can adjust > its rate. It already called a clk_set_rate(rate, 96000000), but this > had no effect, so the clock stayed at reset default 24MHz resulting > in a rather slow timing. This became a problem when commit > "1daa3bc mtd: nand_mxs: Setup timing" introduced EDO timing mode for > faster NAND chips. EDO mode can only work properly for cycle times > < 30ns (at least that's specified in the ONFI spec). 1daa3bc resulted > in sporadic NAND read errors on some boards. Nice work! We have tested this patch on ~10 boards that failed with DMA errors before. None of these boards failed after applying this patch. > Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> Tested-by: Sam Ravnborg <sam@xxxxxxxxxxxx> Sam _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
