On Thu, Aug 18, 2016 at 11:15:33PM +0200, Peter Kardos wrote:
> Hi Sascha,
>
> I may have something. It seems the memory (MMU?) gets "messed" up;
>
> Reading the debug uart registers (v2015.07) gives reasonable results, like
> (gdb) x/32w 0xfffff200
> 0xfffff200: 0x00000000 0x00000800 0x00000000 0x00000000
> 0xfffff210: 0x00000000 0x40001a1a 0x00000000 0x00000000
> 0xfffff220: 0x00000021 0x00000000 0x00000000 0x00000000
> 0xfffff230: 0x00000000 0x00000000 0x00000000 0x00000000
> 0xfffff240: 0x09290781 0x00000000 0x00000000 0x00000000
>
> However the content from v2016.08 gives
>
> 0xFFFFF200 D78D7E1F F1139ADE 413E0FE5 BBFB6DF2
> 0xFFFFF210 7D78666E 79CBDEA6 8FB2CB03 BEF6C2B7
> 0xFFFFF220 C9071D17 FA1EFA2D C4BCD95E 27D73C7C
> 0xFFFFF230 727C3437 DFBDEBED 69C45C2A 7F5958F6
> 0xFFFFF240 834B237E F8B8A211 1AC74D66 FAE06274
Uh, this indeed seems to be messed up by the MMU, more specifically
during setup of the vector table. Could you try the attached patch?
It's not a solution, but is a clear indication that the bug is in this
area.
Sascha
---------------------------8<--------------------------------
>From eb66f09db694a0bc1fc88cde8d86e47faf6debf9 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Date: Mon, 22 Aug 2016 08:05:38 +0200
Subject: [PATCH] ARM: Disable vector table (tmp)
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
arch/arm/cpu/mmu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index a31bce4..fc26077 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -289,6 +289,8 @@ static void create_vector_table(unsigned long adr)
u32 *exc;
int idx;
+ return;
+
vectors_sdram = request_sdram_region("vector table", adr, SZ_4K);
if (vectors_sdram) {
/*
--
2.8.1
--
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