I have already spoken with Sascha about this a bit, but figured I'd throw it out here in case anyone had any suggestions. Specifically, I'm updating the support for the Variscite SOM to handle the newest version of their SOM -- which now includes an EEPROM that contains a "DCD-like" script for configuring the DDR3 timing parameters. Essentially this means that I have to follow a boot procedure similar to that used by the current Wandboard setup, which loads part of barebox into IRAM/OCRAM on the iMX6, read/configures the DDR3 timings, then reloads barebox into DDR3 and starts it. I think I have gotten things more or less setup at this point and have copied the setup from the Wandboard, but am having trouble getting things to actually start from the internal RAM on the board. For now, I have a correct DCD already built-in that preconfigures DDR3 "just in case" and if I set the load address to be DDR3, then everything starts up as normal -- which in and of itself points to a problem. My suspicion is that the boot ROM is still trying to load the full image rather than just part of it -- which means that, when I point it to the IRAM/OCRAM, it is writing to the aliased memory regions of the built in RAM and overwriting itself in the process. What/where actually controls the length of the code that gets automatically loaded by the iMX6 internal boot ROM and what needs to be updated? Any additional suggestions/tips on how to get things working would be greatly appreciated. I feel like I'm close, but simply missing something somewhere. Thanks! Michael Burkey _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
