From: grodriguez <guille.rodriguez@xxxxxxxxx>
Commit da89ee8f2e04 ("Center FLP timing at 16ms") breaks
genphy_restart_aneg() for Micrel's ksz9031. According to the
datasheet, the ksz9031 requires a wait of 1ms after clearing
the PDOWN bit and before read/write access to any PHY registers.
---
drivers/net/phy/phy.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 73176fb..ed69d9b 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -561,7 +561,7 @@ int phy_wait_aneg_done(struct phy_device *phydev)
*/
int genphy_restart_aneg(struct phy_device *phydev)
{
- int ctl;
+ int ctl, pdown;
ctl = phy_read(phydev, MII_BMCR);
@@ -574,6 +574,7 @@ int genphy_restart_aneg(struct phy_device *phydev)
ctl &= ~(BMCR_ISOLATE);
/* Clear powerdown bit which eventually is set on some phys */
+ pdown = ctl & BMCR_PDOWN;
ctl &= ~BMCR_PDOWN;
ctl = phy_write(phydev, MII_BMCR, ctl);
@@ -581,6 +582,12 @@ int genphy_restart_aneg(struct phy_device *phydev)
if (ctl < 0)
return ctl;
+ /* Micrel's ksz9031 (and perhaps others?): Changing the PDOWN bit
+ * from '1' to '0' generates an internal reset. Must wait a minimum
+ * of 1ms before read/write access to the PHY registers. */
+ if (pdown)
+ mdelay(1);
+
return 0;
}
--
1.7.9.5
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