Remove the remnants of the workaround for erratum ERR005184 which was never
completely implemented. The checks alone don't carry any value as we don't
act properly on the result.
A workaround should be added to the lane speed change in establish_link
later.
[Andrey Smirnov: port to Barebox codebase]
Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
---
drivers/pci/pci-imx6.c | 17 +----------------
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index c564a60..ee1a0c5 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -504,7 +504,7 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
static int imx6_pcie_link_up(struct pcie_port *pp)
{
- u32 rc, debug_r0, rx_valid;
+ u32 rc;
int count = 5;
/*
@@ -538,21 +538,6 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
*/
udelay(1000);
}
- /*
- * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
- * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
- * If (MAC/LTSSM.state == Recovery.RcvrLock)
- * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
- * to gen2 is stuck
- */
- pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
- debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
-
- if (rx_valid & 0x01)
- return 0;
-
- if ((debug_r0 & 0x3f) != 0x0d)
- return 0;
return 0;
}
--
2.5.5
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