On i.MX6 a single chipselect can have 4GiB. In this case the calculation
for CS0_end overflows the 7 bit field. Clamp it to 127, the maximum
supported value.
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
arch/arm/mach-imx/imx6-mmdc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
index 146df57..8f661e3 100644
--- a/arch/arm/mach-imx/imx6-mmdc.c
+++ b/arch/arm/mach-imx/imx6-mmdc.c
@@ -1199,7 +1199,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
trcd = trp;
trtp = twtr;
- cs0_end = 4 * sysinfo->cs_density - 1 + 8;
+ cs0_end = min(4 * sysinfo->cs_density - 1 + 8, 127);
debug("density:%d Gb (%d Gb per chip)\n",
sysinfo->cs_density, ddr3_cfg->density);
--
2.7.0
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