Add support for 4bit HW ECC modes supported by later IP versions.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@xxxxxxxxx>
Tested-by: Robert Jarzmik <robert.jarzmik@xxxxxxx>
---
drivers/mtd/nand/nand_mrvl_nfc.c | 65 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index ac1cb3fa9ae3..3e9fccdffefe 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -227,6 +227,31 @@ static struct nand_ecclayout ecc_layout_2KB_hwecc = {
.oobfree = { {0, 40} }
};
+static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
+ .eccbytes = 32,
+ .eccpos = {
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63},
+ .oobfree = { {2, 30} }
+};
+
+static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
+ .eccbytes = 64,
+ .eccpos = {
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63,
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127},
+ /* Bootrom looks in bytes 0 & 5 for bad blocks */
+ .oobfree = { {1, 4}, {6, 26}, {64, 32} }
+};
+
#define NDTR0_tCH(c) (min((c), 7) << 19)
#define NDTR0_tCS(c) (min((c), 7) << 16)
#define NDTR0_tWH(c) (min((c), 7) << 11)
@@ -866,6 +891,43 @@ static int pxa_ecc_strength1(struct mrvl_nand_host *host,
return -ENODEV;
}
+static int pxa_ecc_strength4(struct mrvl_nand_host *host,
+ struct nand_ecc_ctrl *ecc, int ecc_stepsize, int page_size)
+{
+ if (!(host->hwflags & HWFLAGS_ECC_BCH))
+ return -ENODEV;
+
+ /*
+ * Required ECC: 4-bit correction per 512 bytes
+ * Select: 16-bit correction per 2048 bytes
+ */
+ if (ecc_stepsize == 512 && page_size == 2048) {
+ host->chunk_size = 2048;
+ host->spare_size = 32;
+ host->ecc_size = 32;
+ host->ecc_bch = 1;
+ ecc->mode = NAND_ECC_HW;
+ ecc->size = 2048;
+ ecc->layout = &ecc_layout_2KB_bch4bit;
+ ecc->strength = 16;
+ return 0;
+ }
+
+ if (ecc_stepsize == 512 && page_size == 4096) {
+ host->chunk_size = 2048;
+ host->spare_size = 32;
+ host->ecc_size = 32;
+ host->ecc_bch = 1;
+ ecc->mode = NAND_ECC_HW;
+ ecc->size = 2048;
+ ecc->layout = &ecc_layout_4KB_bch4bit;
+ ecc->strength = 16;
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static int pxa_ecc_init(struct mrvl_nand_host *host,
struct nand_ecc_ctrl *ecc,
int strength, int ecc_stepsize, int page_size)
@@ -876,6 +938,9 @@ static int pxa_ecc_init(struct mrvl_nand_host *host,
case 1:
ret = pxa_ecc_strength1(host, ecc, ecc_stepsize, page_size);
break;
+ case 4:
+ ret = pxa_ecc_strength4(host, ecc, ecc_stepsize, page_size);
+ break;
}
if (ret) {
--
2.1.4
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