On Tue, Nov 10, 2015 at 10:44:50PM +0000, Trent Piepho wrote:
> The dw MAC requires that all clock domains to be running for it to
> finish a MAC reset. This include the clock provided by the PHY.
>
> If the PHY is powered down, bit BMCR_PDOWN set, then it won't be
> generating a clock. And so the MAC never comes out of reset. On
> shutdown, Linux will put the PHY in powerdown mode, so it can easily
> be the case that the PHY is powered down on boot.
>
> See Linux kernel commit 2d871aa07136fe6e576bde63072cf33e2c664e95.
>
> Currently the MAC reset is done before the phy is probed. We can't
> power up the phy until it's probed, so the resets must be in the
> opposite order. The MAC reset is in device init but the PHY probe is
> in device open. Device init is done first, always, while open is done
> later, and only if the device is used.
>
> Rather than move the phy probe to init, this moves the MAC reset to
> open. It seems better to speed up boots that don't use ethernet by
> skipping MAC reset than to slow them down by adding PHY probe.
>
> Signed-off-by: Trent Piepho <tpiepho@xxxxxxxxxxxxxx>
> ---
> drivers/net/designware.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> Instead of phy call in the designware driver, it would be nicer to
> use the phylib layer to abstract it. Except that the barebox
> phylib has no support for power management and doesn't need it.
>
> So one either adds general PM support just to clear one bit in one
> register, which seems like a bloated and overly complex solution.
> Or comes up with a generalized method to clear one bit, which seems
> pointless.
I agree, but
>
> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
> index 8006527..7109e97 100644
> --- a/drivers/net/designware.c
> +++ b/drivers/net/designware.c
> @@ -218,6 +218,16 @@ static int dwc_ether_init(struct eth_device *dev)
> struct dw_eth_dev *priv = dev->priv;
> struct eth_mac_regs *mac_p = priv->mac_regs_p;
> struct eth_dma_regs *dma_p = priv->dma_regs_p;
> + int bmcr;
> +
> + /* Before we reset the mac, we must insure the PHY is not powered down
> + * as the dw controller needs all clock domains to be running, including
> + * the PHY clock, to come out of a mac reset. */
> + bmcr = phy_read(dev->phydev, MII_BMCR);
> + if (bmcr & BMCR_PDOWN) {
> + bmcr &= ~BMCR_PDOWN;
> + phy_write(dev->phydev, MII_BMCR, bmcr);
> + }
Could you factor out this code to a separate function which you name
phy_resume()? This way, should we ever need this functionality again we
hopefully stumble upon this and can revisit this.
Sascha
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