U-Boot uses 2 as the DSS divider, so do the same in barebox. This shouldn't currently have any effect to barebox, but makes porting some U-Boot code easier which makes assumptions about the DSS clock rate. Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- arch/arm/mach-omap/include/mach/omap3-clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h index 1ef46aa..7c52da7 100644 --- a/arch/arm/mach-omap/include/mach/omap3-clock.h +++ b/arch/arm/mach-omap/include/mach/omap3-clock.h @@ -107,7 +107,7 @@ /* PER DPLL */ #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -#define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ +#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) -- 2.1.4 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
