This errata workaround was introduced for i.MX6Q, i.MX6D and i.MX6SL.
Old revisions of i.MX6s chips had no problems with the PFD resets.
In a newer i.MX6s revision I had issues with this code when booting in
internal boot mode from NAND or in serial downloader mode. FUSE mode
worked fine although it jumped directly to serial downloader mode.
This patch executes the PFD workaround only for i.MX6Q and i.MX6D which
fixes the issues I saw.
Signed-off-by: Markus Pargmann <mpa@xxxxxxxxxxxxxx>
---
arch/arm/mach-imx/imx6.c | 48 +++++++++++++++++++++++++-----------------------
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 73630e70927a..7508964bf549 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -30,7 +30,8 @@ void imx6_init_lowlevel(void)
void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
- int is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
+ bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
+ bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
uint32_t val;
/*
@@ -67,28 +68,29 @@ void imx6_init_lowlevel(void)
* not output clock after reset, MX6DL and MX6SL have added 396M pfd
* workaround in ROM code, as bus clock need it
*/
- writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
- BM_ANADIG_PFD_480_PFD2_CLKGATE |
- BM_ANADIG_PFD_480_PFD1_CLKGATE |
- BM_ANADIG_PFD_480_PFD0_CLKGATE,
- MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
- writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
- (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
- BM_ANADIG_PFD_528_PFD1_CLKGATE |
- BM_ANADIG_PFD_528_PFD0_CLKGATE,
- MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
-
- writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
- BM_ANADIG_PFD_480_PFD2_CLKGATE |
- BM_ANADIG_PFD_480_PFD1_CLKGATE |
- BM_ANADIG_PFD_480_PFD0_CLKGATE,
- MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
- writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
- (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
- BM_ANADIG_PFD_528_PFD2_CLKGATE |
- BM_ANADIG_PFD_528_PFD1_CLKGATE |
- BM_ANADIG_PFD_528_PFD0_CLKGATE,
- MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
+ if (is_imx6q || is_imx6d) {
+ writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
+ BM_ANADIG_PFD_480_PFD2_CLKGATE |
+ BM_ANADIG_PFD_480_PFD1_CLKGATE |
+ BM_ANADIG_PFD_480_PFD0_CLKGATE,
+ MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
+ writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
+ (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+ BM_ANADIG_PFD_528_PFD1_CLKGATE |
+ BM_ANADIG_PFD_528_PFD0_CLKGATE,
+ MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
+
+ writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
+ BM_ANADIG_PFD_480_PFD2_CLKGATE |
+ BM_ANADIG_PFD_480_PFD1_CLKGATE |
+ BM_ANADIG_PFD_480_PFD0_CLKGATE,
+ MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
+ writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
+ (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+ BM_ANADIG_PFD_528_PFD1_CLKGATE |
+ BM_ANADIG_PFD_528_PFD0_CLKGATE,
+ MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
+ }
val = readl(iomux + IOMUXC_GPR4);
val |= IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL |
--
2.1.4
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