In PCI 64-bit BARs span two 32-bit BARs, therefore if BAR type
indicates a 64-bit BAR we have to skip the next BAR register.
Note that this does not add proper support for 64-bit BARs and
64-bit addresses but still picks the lower 32-bit address.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@xxxxxxxxx>
---
To: barebox@xxxxxxxxxxxxxxxxxxx
To: Sebastian Hesselbarth <sebastian.hesselbarth@xxxxxxxxx>
Cc: Antony Pavlov <antonynpavlov@xxxxxxxxx>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@xxxxxxxxxxxx>
Cc: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxxxxxxxxx>
Cc: Ezequiel Garcia <ezequiel.garcia@xxxxxxxxxxxxxxxxxx>
---
drivers/pci/pci.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3d88b0ff5fd0..e5cd8a33b2be 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -196,6 +196,7 @@ unsigned int pci_scan_bus(struct pci_bus *bus)
for (bar = 0; bar < 6; bar++) {
resource_size_t last_addr;
+ bool found_bar64 = false;
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, &old_bar);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, 0xfffffffe);
@@ -213,17 +214,22 @@ unsigned int pci_scan_bus(struct pci_bus *bus)
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io);
last_addr = last_io;
last_io += size;
-
} else { /* MEM */
size = -(mask & 0xfffffff0);
DBG(" PCI: pbar%d: mask=%08x memory %d bytes\n", bar, mask, size);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem);
last_addr = last_mem;
last_mem += size;
+
+ if ((mask & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ PCI_BASE_ADDRESS_MEM_TYPE_64)
+ found_bar64 = true;
}
dev->resource[bar].start = last_addr;
dev->resource[bar].end = last_addr + size - 1;
+ if (found_bar64)
+ bar++;
}
}
--
2.0.0
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