This isn't much different from the default 1,16V
and I haven't seen this make a difference on any
board, but it seems to be required for some T30 SKUs.
Signed-off-by: Lucas Stach <dev@xxxxxxxxxx>
---
arch/arm/boards/nvidia-beaver/entry.c | 1 +
arch/arm/mach-tegra/include/mach/lowlevel-dvc.h | 18 ++++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boards/nvidia-beaver/entry.c b/arch/arm/boards/nvidia-beaver/entry.c
index 25452a6..576fcb7 100644
--- a/arch/arm/boards/nvidia-beaver/entry.c
+++ b/arch/arm/boards/nvidia-beaver/entry.c
@@ -30,6 +30,7 @@ ENTRY_FUNCTION(start_nvidia_beaver, r0, r1, r2)
tegra_cpu_lowlevel_setup();
tegra_dvc_init();
+ tegra30_tps62366a_ramp_vddcore();
tegra30_tps65911_cpu_rail_enable();
fdt = (uint32_t)__dtb_tegra30_beaver_start - get_runtime_offset();
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
index f7f6328..32f10d7 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
@@ -70,3 +70,21 @@ void tegra30_tps65911_cpu_rail_enable(void)
tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES);
tegra_ll_delay_usec(10 * 1000);
}
+
+static inline __attribute__((always_inline))
+void tegra30_tps62366a_ramp_vddcore(void)
+{
+ tegra_dvc_write_addr(0xc0, 2);
+ /* set VDDcore to 1,2V */
+ tegra_dvc_write_data(0x4601, TEGRA_I2C_SEND_2_BYTES);
+ tegra_ll_delay_usec(1000);
+}
+
+static inline __attribute__((always_inline))
+void tegra30_tps62361b_ramp_vddcore(void)
+{
+ tegra_dvc_write_addr(0xc0, 2);
+ /* set VDDcore to 1,2V */
+ tegra_dvc_write_data(0x4603, TEGRA_I2C_SEND_2_BYTES);
+ tegra_ll_delay_usec(1000);
+}
--
1.9.0
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