Avoids glitches in later starup phases. Signed-off-by: Lucas Stach <dev@xxxxxxxxxx> --- arch/arm/mach-tegra/include/mach/tegra20-car.h | 4 ++++ arch/arm/mach-tegra/tegra_avp_init.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h index a5441de..161e3d8 100644 --- a/arch/arm/mach-tegra/include/mach/tegra20-car.h +++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h @@ -112,6 +112,10 @@ #define CRC_SUPER_SDIV_DIVISOR_SHIFT 0 #define CRC_SUPER_SDIV_DIVISOR_MASK (0xff << CRC_SUPER_SDIV_DIVISOR_SHIFT) +#define CRC_CLK_SYSTEM_RATE 0x030 +#define CRC_CLK_SYSTEM_RATE_AHB_SHIFT 4 +#define CRC_CLK_SYSTEM_RATE_APB_SHIFT 0 + #define CRC_CLK_CPU_CMPLX 0x04c #define CRC_CLK_CPU_CMPLX_CPU3_CLK_STP (1 << 11) #define CRC_CLK_CPU_CMPLX_CPU2_CLK_STP (1 << 10) diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c index 9f8ccf3..4dd1330 100644 --- a/arch/arm/mach-tegra/tegra_avp_init.c +++ b/arch/arm/mach-tegra/tegra_avp_init.c @@ -149,6 +149,9 @@ static void start_cpu0_clocks(void) TEGRA_CLK_RESET_BASE + CRC_SCLK_BURST_POLICY); writel(CRC_SUPER_SDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_SCLK_DIV); + writel(1 << CRC_CLK_SYSTEM_RATE_AHB_SHIFT, + TEGRA_CLK_RESET_BASE + CRC_CLK_SYSTEM_RATE); + /* deassert clock stop for cpu 0 */ reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX); reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP; -- 1.8.5.3 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
