Fix the chip select configuration register offset increment and summing
of bank size so that, for chip select index greater than 0, barebox can
determine the total memory size from enabled banks.
Signed-off-by: Renaud Barbier <renaud.barbier@xxxxxx>
---
arch/ppc/mach-mpc85xx/cpu.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/mach-mpc85xx/cpu.c b/arch/ppc/mach-mpc85xx/cpu.c
index 17a1c4c..e5c01fc 100644
--- a/arch/ppc/mach-mpc85xx/cpu.c
+++ b/arch/ppc/mach-mpc85xx/cpu.c
@@ -68,14 +68,14 @@ phys_size_t fsl_get_effective_memsize(void)
sdram_size = 0;
for (ix = 0; ix < CFG_CHIP_SELECTS_PER_CTRL; ix++) {
- if (in_be32(regs + DDR_OFF(CS0_CONFIG) + (ix * 8)) &
+ if (in_be32(regs + DDR_OFF(CS0_CONFIG) + (ix * 4)) &
SDRAM_CFG_MEM_EN) {
reg = in_be32(regs + DDR_OFF(CS0_BNDS) + (ix * 8));
/* start address */
san = (reg & 0x0fff00000) >> 16;
/* end address */
ean = (reg & 0x00000fff);
- sdram_size = ((ean - san + 1) << 24);
+ sdram_size += ((ean - san + 1) << 24);
}
}
--
1.7.1
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