The correct DDRPLL for PCM051 is 303MHz. Signed-off-by: Teresa Gámez <t.gamez@xxxxxxxxx> --- As the board runs also fine with 266MHz. There is no need to fix it in master. arch/arm/boards/pcm051/lowlevel.c | 2 +- arch/arm/mach-omap/include/mach/am33xx-clock.h | 1 + 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/arm/boards/pcm051/lowlevel.c b/arch/arm/boards/pcm051/lowlevel.c index 078e83b..48578cd 100644 --- a/arch/arm/boards/pcm051/lowlevel.c +++ b/arch/arm/boards/pcm051/lowlevel.c @@ -68,7 +68,7 @@ static int pcm051_board_init(void) if (running_in_sdram()) return 0; - pll_init(MPUPLL_M_600, 25, DDRPLL_M_266); + pll_init(MPUPLL_M_600, 25, DDRPLL_M_303); am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd, &MT41J256M8HX15E_2x256M8_regs, diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index b3c7519..ecd90b2 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -49,6 +49,7 @@ /* DDR Freq is 266 MHZ for now*/ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ #define DDRPLL_M_266 266 +#define DDRPLL_M_303 303 #define DDRPLL_M_400 400 #define DDRPLL_N (OSC - 1) #define DDRPLL_M2 1 -- 1.7.0.4 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
