Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> writes: >> Coupling the -mno-unaligned-access to the TEXT_BASE and the used processor >> might be a better solution. > > No, unaligned accesses are handled by the cache. They won't work when > the MMU is disabled, but barebox has to work with MMU disabled. ok; this stuff seems to be really processor dependent then. E.g. unaligned access works on Cortex-M3 which is ARMv7 but has neither an MMU nor an MPU. Perhaps 'CONFIG_ARM_NOUNALIGNED' should default to yes when !MMU, and/or it should be selected by other problematic configurations. Of course, there is still the problem that some C code is executed before MMU will be enabled and unaligned access can happen there. While thinking about it... cause of the core problem (unaligned access exception when executed in SRAM) might be that SRAM memory mapped as strongly ordered memory: | :/ mmuinfo 0x40300000 | ... | Inner mem. attr. [6:4]: 0x1 (0b001 Strongly-ordered) Perhaps, this memory can be remapped as normal memory. Enrico _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
