Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- arch/arm/boards/phycard-i.MX27/lowlevel_init.S | 1 + arch/arm/mach-imx/include/mach/imx27-regs.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S index 8f0000f..38cc55c 100644 --- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S +++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S @@ -7,6 +7,7 @@ #include <config.h> #include <mach/imx27-regs.h> #include <mach/imx-pll.h> +#include <mach/esdctl.h> #include <asm/barebox-arm-head.h> #define writel(val, reg) \ diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h index 90b4614..44bc1d3 100644 --- a/arch/arm/mach-imx/include/mach/imx27-regs.h +++ b/arch/arm/mach-imx/include/mach/imx27-regs.h @@ -124,8 +124,6 @@ #define MX27_WBCR 0x1C /* Well Bias Control Register */ #define MX27_DSCR(x) (0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ -#include "esdctl.h" - /* PLL registers (base: MX27_CCM_BASE_ADDR) */ #define MX27_CSCR 0x00 /* Clock Source Control Register */ #define MX27_MPCTL0 0x04 /* MCU PLL Control Register 0 */ -- 1.7.10.4 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
