On Mon, Oct 15, 2012 at 07:58:52PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 20:26 Mon 15 Oct , Alexander Shiyan wrote:
> >
> > +
> > +#define UBRLCR(x) (UBRLCR1 + (x) * 0x1000)
> > +#define SYSCON(x) (SYSCON1 + (x) * 0x1000)
> > +#define SYSFLG(x) (SYSFLG1 + (x) * 0x1000)
> > +#define UARTDR(x) (UARTDR1 + (x) * 0x1000)
> provide this via resoure
>
> here 4 resources
We already had this. This SoC has a very strange register layout. The
registers for the UARTs are spread around the SoC and the registers
are not even exclusively used for the UARTs. They have bits which are
also used for the timer and other stuff.
> > +static int clps711x_tstc(struct console_device *cdev)
> > +{
> > + return !(readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE);
> factorise those pull status as
>
> status int xxx(data, mask) {}
I don'r understand this. This is a single register read, there's not
much to factorize and the code is easy to read.
Sascha
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