+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <io.h>
+#include <gpio.h>
+#include <init.h>
+#include <mach/platform.h>
+
+#define GPIOFSEL(x) (0x00+(x)*4)
+#define GPIOSET(x) (0x1c+(x)*4)
+#define GPIOCLR(x) (0x28+(x)*4)
+#define GPIOLEV(x) (0x34+(x)*4)
+#define GPIOEDS(x) (0x40+(x)*4)
+#define GPIOREN(x) (0x4c+(x)*4)
+#define GPIOFEN(x) (0x58+(x)*4)
+#define GPIOHEN(x) (0x64+(x)*4)
+#define GPIOLEN(x) (0x70+(x)*4)
+#define GPIOAREN(x) (0x7c+(x)*4)
+#define GPIOAFEN(x) (0x88+(x)*4)
+#define GPIOUD(x) (0x94+(x)*4)
+#define GPIOUDCLK(x) (0x98+(x)*4)
+
+enum {
+ GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
+ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
+ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
+ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
+};
+
+struct bcm2835_gpio_chip {
+ void __iomem *base;
+ struct gpio_chip chip;
+};
+
+static int bcm2835_set_function(struct gpio_chip *chip, unsigned gpio, int function)
+{
you should add one bank pre gpio_chip
+ struct bcm2835_gpio_chip *bcmgpio = container_of(chip, struct bcm2835_gpio_chip, chip);
+ void __iomem *base = bcmgpio->base;
+ unsigned gpiodir;
+ unsigned gpio_bank = gpio / 10;
+ unsigned gpio_field_offset = (gpio - 10 * gpio_bank) * 3;
so this will be dropped
+
+ gpiodir = readl(base + GPIOFSEL(gpio_bank));
+ gpiodir &= ~(7 << gpio_field_offset);
+ gpiodir |= function << gpio_field_offset;
+ writel(gpiodir, base + GPIOFSEL(gpio_bank));
+ gpiodir = readl(base + GPIOFSEL(gpio_bank));
+
+ return 0;
+}
+
Uhm, this could be not convenient since the two banks in BCM2835 are not really separated, there are not exclusive registers for one bank or for the other. The registers used for GPIOs configuration manage both the two banks (see for example GPFSELx). If I add one bank I can avoid calculating the bank offset for GPCLRx and GPSETx but not for GPFSELx and viceversa (in fact in the code I select the bank for GPCLRx and GPSETx with gpio_bank = gpio / 32 whereas for GPIOFSEL with gpio_bank = gpio / 10). Yay, confusing …
Best,
-- Carlo Caione |
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