Hi > arch/arm/mach-imx/clk-imx25.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c > index 3b9588c..3a141c2 100644 > --- a/arch/arm/mach-imx/clk-imx25.c > +++ b/arch/arm/mach-imx/clk-imx25.c > @@ -76,9 +76,19 @@ static int imx25_ccm_probe(struct device_d *dev) > > base = dev_request_mem_region(dev, 0); > > - writel(0x10e88578, base + CCM_CGCR0); > - writel(0x0478e1e0, base + CCM_CGCR0); > - writel(0x0007c400, base + CCM_CGCR0); > + writel((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 9) | > + (1 << 10) | (1 << 15) | (1 << 19) | (1 << 21) | (1 << 22) | > + (1 << 22) | (1 << 23) | (1 << 24) | (1 << 28), (1<<22) does not need to be written twice, I'm sure the bit is safe in silicon :). > + base + CCM_CGCR0); > + > + writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) | > + (1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) | > + (1 << 26) | (1 << 29) | (1 << 31), > + base + CCM_CGCR1); > + > + writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) | > + (1 << 15) | (1 << 16) | (1 << 17) | (1 << 18), > + base + CCM_CGCR2); Quite a change from writing 0x15692B58 (sum) to CGCR0, enabling PER clocks esdhc1, esdhc2, i2c, nfc, owire, sim1, ssi1, and AHB clocks ata, emi, esdhc1, esdhc2, lcdc, sdma, usbotg, to now enabling the following clocks: PER: esdhc1, esdhc2, i2c, nfc, owire, pwm(!), uart (!) AHB: emi, esdhc1, esdhc2, fec, lcdc, usbotg Why not enable all clocks (i.e. sim1, sim2, ssi1, ssi2)? Maybe because we have no drivers (yet)? Or does it not matter, because each platform driver is required to set the clocks anyway in the init routine? With regard to CGCR1 and CGCR2, the following clock outputs get enabled (maybe for changelog): IPG: cspi1, cspi2, cspi3, esdhc1, esdhc2, fec, gpt1, gpt2, gpt3, gpt4, iim, LCDC_EN, pwm1, pwm2, pwm3, pwm4, spba, tsc, uart1, uart2, uart3, uart4, uart5. Cheers Roberto _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
