Hi Johannes, On Thu, Sep 27, 2012 at 12:33:23PM +0200, Johannes Stezenbach wrote: > On Thu, Sep 27, 2012 at 11:53:12AM +0200, Sascha Hauer wrote: > > On Thu, Sep 27, 2012 at 12:56:46AM +0200, Uwe Kleine-König wrote: > > > > > > 2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or > > > system reset, any 2-wire part can be reset by following these steps: > > > (a) Create a start bit condition, > > > (b) Clock 9 cycles, > > > (c) Create another start bit followed by a stop bit condition as > > > shown below. The device is ready for the next communication > > > after the above steps have been completed. > > > > > > SCL /¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\ > > > SDA ¯\_/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯\___/¯ > > > S 1 2 3 4 5 6 7 8 9 Sr P > > > > > > > Sounds good. We often have this problem. > > > > I wonder if it's worth to have this as a general callback in the i2c > > layer. > > I wonder how this relates to the SW reset and Bus Clear > procedures from the I2C spec? > http://www.nxp.com/documents/user_manual/UM10204.pdf Software reset seems to start with sending address 0 (general call address) and not being supported by all devices. Bus Clear is roughly what I implemented. As I understand it the I2C-bus specification doesn't put the S, Sr and P around the clock. > I think the above is not a SW reset, essentially it > sends 9 clocks to make the slave release SDA and then > it sends a STOP to get the bus into an idle state. ... depends on the definition of SW reset. It's definitily not the same thing as in the I2C-bus spec. So choosing a different name would be good. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
