According to a comment in Linux' fec driver, i.MX28 uses the same
formula for determination of the frequency divider as i.MX6, that is
(different from the i.MX28 manual):
parent clock / ((MII_SPEED + 1) * 2)
instead of
parent clock / (MII_SPEED * 2)
on the older i.MX SoCs. Fix the calculation accordingly.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>
--
But note that this doesn't fix accessing the phy on my machine. The
calculated value is 9 (with and without this patch btw) but accessing
the phy only gets reliable with a value of >=20 or alternatively don't
set the SPEED value before reading and writing a mii register but only
on probe.
The Freescale kernel 2.6.35_10.12.01 does the following instead (in
fec_switch.c):
fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
#ifdef CONFIG_ARCH_MXS
/* Can't get phy(8720) ID when set to 2.5M on MX28, lower it */
fep->phy_speed <<= 2;
#endif
which would result in 40 (and is unaware of the changed formula).
I didn't have an opportunity to check the signals with an oszilloscope, but
intend to fetch that later.
---
drivers/net/fec_imx.c | 48 ++++++++++++++++++++++++++++++++++++++----------
1 file changed, 38 insertions(+), 10 deletions(-)
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 599a9b4..969c903 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -47,6 +47,41 @@ struct fec_frame {
uint8_t head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
};
+static void fec_miidev_setspeed(struct fec_priv *fec)
+{
+ u32 mii_speed;
+
+ mii_speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
+
+#ifdef CONFIG_ARCH_MXS
+ /*
+ * Compared to the other imx socs imx28 and imx6 have an additional "+1"
+ * in the formula for MII_SPEED. In MCIMX28RM Rev.1, 2010 this is not
+ * documented though.
+ */
+ mii_speed -= 1;
+#endif
+ if (!mii_speed)
+ /* Can this happen? */
+ mii_speed = 1;
+ if (mii_speed > 0x3f) {
+ static int once = 0;
+ if (!once)
+ printf("Warning: fec clk too high to get mii clk\n");
+ mii_speed = 0x3f;
+ }
+
+ /*
+ * XXX: some SoCs (at least i.MX28 and i.MX6, but not .iMX27) have an
+ * bitfield in ENET_MSCR (aka MII_SPEED) called HOLDTIME that needs to
+ * be >0 for imx_get_fecclk() > 100 MHz.
+ */
+
+ writel(mii_speed << 1, fec->regs + FEC_MII_SPEED);
+
+ return 0;
+}
+
/*
* MII-interface related functions
*/
@@ -59,8 +94,7 @@ static int fec_miidev_read(struct mii_device *mdev, int phyAddr, int regAddr)
uint32_t phy; /* convenient holder for the PHY */
uint64_t start;
- writel(((imx_get_fecclk() >> 20) / 5) << 1,
- fec->regs + FEC_MII_SPEED);
+ fec_miidev_setspeed(fec);
/*
* reading from any PHY's register is done by properly
* programming the FEC's MII data register.
@@ -103,8 +137,7 @@ static int fec_miidev_write(struct mii_device *mdev, int phyAddr,
uint32_t phy; /* convenient holder for the PHY */
uint64_t start;
- writel(((imx_get_fecclk() >> 20) / 5) << 1,
- fec->regs + FEC_MII_SPEED);
+ fec_miidev_setspeed(fec);
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
@@ -292,12 +325,7 @@ static int fec_init(struct eth_device *dev)
rcntl = FEC_R_CNTRL_MAX_FL(1518);
if (fec->xcv_type != SEVENWIRE) {
rcntl |= FEC_R_CNTRL_MII_MODE;
- /*
- * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
- * and do not drop the Preamble.
- */
- writel(((imx_get_fecclk() >> 20) / 5) << 1,
- fec->regs + FEC_MII_SPEED);
+ fec_miidev_setspeed(fec);
}
if (fec->xcv_type == RMII) {
--
1.7.10.4
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