- get USB PHY clock from OSC (24MHz) - adjust USB clock to 54MHz Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- arch/arm/mach-imx/imx53.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c index 8742c46..b5dbc39 100644 --- a/arch/arm/mach-imx/imx53.c +++ b/arch/arm/mach-imx/imx53.c @@ -154,10 +154,15 @@ void imx53_init_lowlevel(unsigned int cpufreq_mhz) writel(0x00016154, ccm + MX5_CCM_CBCMR); - /* change uart clk parent to pll2 */ r = readl(ccm + MX5_CCM_CSCMR1); - r &= ~(3 << 24); - r |= (1 << 24); + + /* change uart clk parent to pll2 */ + r &= ~MX5_CCM_CSCMR1_UART_CLK_SEL_MASK; + r |= 1 << MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + + /* USB phy clock from osc */ + r &= ~(1 << MX5_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET); + writel(r, ccm + MX5_CCM_CSCMR1); /* make sure change is effective */ @@ -187,6 +192,12 @@ void imx53_init_lowlevel(unsigned int cpufreq_mhz) r &= ~MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK; r |= 1 << MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET; + r &= ~MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; + r &= ~MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; + + r |= 3 << MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; + r |= 1 << MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; + writel(r, ccm + MX5_CCM_CSCDR1); /* Restore the default values in the Gate registers */ -- 1.7.10 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
