The previous code assumed pll2 which is correct when we set the uart parent to pll2 beforehand. The reset default is different though, so calculate uart parent based on hardware setting. Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- arch/arm/mach-imx/speed-imx51.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c index 643ad8f..84f4892 100644 --- a/arch/arm/mach-imx/speed-imx51.c +++ b/arch/arm/mach-imx/speed-imx51.c @@ -115,7 +115,15 @@ unsigned long imx_get_uartclk(void) u32 reg, prediv, podf; unsigned long parent_rate; - parent_rate = pll2_sw_get_rate(); + reg = ccm_readl(MX5_CCM_CSCMR1); + reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK; + reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + + parent_rate = get_rate_select(reg, + pll1_main_get_rate, + pll2_sw_get_rate, + pll3_sw_get_rate, + NULL); reg = ccm_readl(MX5_CCM_CSCDR1); prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >> -- 1.7.9.1 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
