- support NAND external boot
- update internal boot init sequence
- unbreak flash_header using magic values ...
- LCD enable
- add I2C
- add SDCard
- add USB Host
- add DFU on USB OTG
Signed-off-by: Eric BÃnard <eric@xxxxxxxxxx>
---
arch/arm/boards/eukrea_cpuimx35/env/bin/init | 4 +-
arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c | 99 ++++++++++++++++++++-
arch/arm/boards/eukrea_cpuimx35/flash_header.c | 22 +++---
arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 20 +++--
arch/arm/configs/eukrea_cpuimx35_defconfig | 14 +++-
5 files changed, 135 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/init b/arch/arm/boards/eukrea_cpuimx35/env/bin/init
index 90007cd..b56d7b5 100644
--- a/arch/arm/boards/eukrea_cpuimx35/env/bin/init
+++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/init
@@ -15,12 +15,12 @@ fi
if [ -f /env/logo.bmp ]; then
fb0.enable=1
bmp /env/logo.bmp
- gpio_direction_out 1 1
+ gpio_set_value 1 1
elif [ -f /env/logo.bmp.lzo ]; then
unlzo /env/logo.bmp.lzo /logo.bmp
fb0.enable=1
bmp /logo.bmp
- gpio_direction_out 1 1
+ gpio_set_value 1 1
fi
if [ -z $eth0.ethaddr ]; then
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 63d019a..7d85f97 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -51,6 +51,8 @@
#include <mach/pmic.h>
#include <mach/imx-ipu-fb.h>
#include <mach/imx-pll.h>
+#include <i2c/i2c.h>
+#include <usb/fsl_usb2.h>
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
@@ -126,6 +128,70 @@ static struct device_d imxfb_dev = {
.platform_data = &ipu_fb_data,
};
+static struct device_d i2c_dev = {
+ .id = -1,
+ .name = "i2c-imx",
+ .map_base = IMX_I2C1_BASE,
+};
+
+static struct device_d esdhc_dev = {
+ .name = "imx-esdhc",
+ .map_base = IMX_SDHC1_BASE,
+};
+
+#ifdef CONFIG_USB
+
+#define MX35_H1_SIC_SHIFT 21
+#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PM_BIT (1 << 8)
+#define MX35_H1_IPPUE_UP_BIT (1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX35_H1_TLL_BIT (1 << 5)
+#define MX35_H1_USBTE_BIT (1 << 4)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
+
+static void imx35_usb_init(void)
+{
+ unsigned int tmp;
+
+ /* Host 1 */
+ tmp = readl(IMX_OTG_BASE + 0x600);
+ tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+ MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+ tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
+ tmp |= MX35_H1_USBTE_BIT;
+ tmp |= MX35_H1_IPPUE_DOWN_BIT;
+ writel(tmp, IMX_OTG_BASE + 0x600);
+
+ tmp = readl(IMX_OTG_BASE + 0x584);
+ tmp |= 3 << 30;
+ writel(tmp, IMX_OTG_BASE + 0x584);
+
+ /* Set to Host mode */
+ tmp = readl(IMX_OTG_BASE + 0x5a8);
+ writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
+}
+
+static struct device_d usbh2_dev = {
+ .id = -1,
+ .name = "ehci",
+ .map_base = IMX_OTG_BASE + 0x400,
+ .size = 0x200,
+};
+#endif
+
+static struct fsl_usb2_platform_data usb_pdata = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+};
+
+static struct device_d usbotg_dev = {
+ .name = "fsl-udc",
+ .map_base = IMX_OTG_BASE,
+ .size = 0x200,
+ .platform_data = &usb_pdata,
+};
+
#ifdef CONFIG_MMU
static int eukrea_cpuimx35_mmu_init(void)
{
@@ -153,6 +219,8 @@ postcore_initcall(eukrea_cpuimx35_mmu_init);
static int eukrea_cpuimx35_devices_init(void)
{
+ unsigned int tmp;
+
register_device(&nand_dev);
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
@@ -165,6 +233,18 @@ static int eukrea_cpuimx35_devices_init(void)
register_device(&sdram_dev);
register_device(&imxfb_dev);
+ register_device(&i2c_dev);
+ register_device(&esdhc_dev);
+
+#ifdef CONFIG_USB
+ imx35_usb_init();
+ register_device(&usbh2_dev);
+#endif
+ /* Workaround ENGcm09152 */
+ tmp = readl(IMX_OTG_BASE + 0x608);
+ writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
+ register_device(&usbotg_dev);
+
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35);
@@ -211,6 +291,16 @@ static struct pad_desc eukrea_cpuimx35_pads[] = {
MX35_PAD_LD23__GPIO3_29,
MX35_PAD_CONTRAST__GPIO1_1,
MX35_PAD_D3_CLS__GPIO1_4,
+
+ MX35_PAD_I2C1_CLK__I2C1_SCL,
+ MX35_PAD_I2C1_DAT__I2C1_SDA,
+
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
};
static int eukrea_cpuimx35_console_init(void)
@@ -219,7 +309,7 @@ static int eukrea_cpuimx35_console_init(void)
ARRAY_SIZE(eukrea_cpuimx35_pads));
/* screen default on to prevent flicker */
- gpio_direction_output(4, 1);
+ gpio_direction_output(4, 0);
/* backlight default off */
gpio_direction_output(1, 0);
/* led default off */
@@ -235,10 +325,15 @@ static int eukrea_cpuimx35_core_init(void)
{
u32 reg;
- /* enable clock for I2C1 and FEC */
+ /* enable clock for I2C1, SDHC1, USB and FEC */
reg = readl(IMX_CCM_BASE + CCM_CGR1);
reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
+ reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT;
+ reg |= 0x3 << CCM_CGR1_I2C1_SHIFT,
reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
+ reg = readl(IMX_CCM_BASE + CCM_CGR2);
+ reg |= 0x3 << CCM_CGR2_USB_SHIFT;
+ reg = writel(reg, IMX_CCM_BASE + CCM_CGR2);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
diff --git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
index 285a2d4..4163caf 100644
--- a/arch/arm/boards/eukrea_cpuimx35/flash_header.c
+++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
@@ -12,24 +12,24 @@ void __naked __flash_header_start go(void)
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
{ .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
- { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x0009572B, },
- { .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, },
+ { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0009572B, },
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92220000, },
{ .ptr_type = 1, .addr = 0x80000400, .val = 0xda, },
- { .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, },
- { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
- { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
- { .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, },
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2220000, },
+ { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
+ { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2220000, },
{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },
- { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82224080, },
- { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82224080, },
+ { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
};
-
+#define DEST_BASE 0x80000000
struct imx_flash_header __flash_header_section flash_header = {
- .app_code_jump_vector = DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE),
+ .app_code_jump_vector = DEST_BASE + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index aad334d..6c0e106 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -66,6 +66,7 @@ void __bare_init __naked board_init_lowlevel(void)
unsigned int *trg, *src;
int i;
#endif
+ register uint32_t loops = 0x20000;
r = get_cr();
r |= CR_Z; /* Flow prediction (Z) */
@@ -118,7 +119,7 @@ void __bare_init __naked board_init_lowlevel(void)
writel(r, ccm_base + CCM_CGR0);
r = readl(ccm_base + CCM_CGR1);
- r |= 0x00000C00;
+ r |= 0x00030C00;
r |= 0x00000003;
writel(r, ccm_base + CCM_CGR1);
@@ -132,31 +133,34 @@ void __bare_init __naked board_init_lowlevel(void)
board_init_lowlevel_return();
/* Init Mobile DDR */
+ writel(0x0000000E, ESDMISC);
writel(0x00000004, ESDMISC);
- writel(0x0000000C, ESDMISC);
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+
writel(0x0009572B, ESDCFG0);
writel(0x92220000, ESDCTL0);
writeb(0xda, IMX_SDRAM_CS0 + 0x400);
writel(0xA2220000, ESDCTL0);
- writel(0x87654321, IMX_SDRAM_CS0);
- writel(0x87654321, IMX_SDRAM_CS0);
+ writeb(0xda, IMX_SDRAM_CS0);
+ writeb(0xda, IMX_SDRAM_CS0);
writel(0xB2220000, ESDCTL0);
writeb(0xda, IMX_SDRAM_CS0 + 0x33);
writeb(0xda, IMX_SDRAM_CS0 + 0x2000000);
- writel(0x82224080, ESDCTL0);
- writel(0x00000004, ESDMISC);
+ writel(0x82228080, ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x1000)
+ if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
/* Move ourselves out of NFC SRAM */
- for (i = 0; i < 0x1000 / sizeof(int); i++)
+ for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig
index 975d095..af82827 100644
--- a/arch/arm/configs/eukrea_cpuimx35_defconfig
+++ b/arch/arm/configs/eukrea_cpuimx35_defconfig
@@ -8,8 +8,11 @@ CONFIG_MALLOC_SIZE=0x800000
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
+# CONFIG_CONSOLE_ACTIVATE_FIRST is not set
+CONFIG_CONSOLE_ACTIVATE_ALL=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx35/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
@@ -22,6 +25,7 @@ CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_RESET=y
@@ -31,15 +35,23 @@ CONFIG_CMD_PARTITION=y
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
+CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
-CONFIG_NAND_IMX_BOOT=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_GADGET=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX_IPU=y
+CONFIG_MCI=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_MCI_IMX_ESDHC_PIO=y
--
1.7.0.4
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