On Tue, Aug 17, 2010 at 05:40:09AM -0500, Nishanth Menon wrote: > On 08/17/2010 03:55 AM, Michael Grzeschik wrote: >> Signed-off-by: Michael Grzeschik<m.grzeschik@xxxxxxxxxxxxxx> >> --- >> This will only work once and bring the nand chip into a undefined state >> after a second call. Any ideas for doing this save? > looking at the gpmc logic, it does a reset in gpmc_cs_config by > disabling and re-enabling it -> so my guess is: > a) in the selection of ecc logic > b) reset of statemachines in mtd layers > c) nand chip not being reset from it's previous state (resetting the > controller does not mean nand chip is reset) (if i recollect sometime > back mtd used to do a 0xff and reset).. > > > personally, IMHO using s/w ecc has not much benefit other than being > "legacy enabled" It really seems odd to me that the omap internal ROM code expects hw ecc while xloader and kernel expect hw ecc. This way we always need two different ecc algorithms in place which is really inconvenient and hard for users to get it right. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
