internal boot : dcd update for mDDR init (relaxed timings)
NAND boot update : mDDR init updated (optimized timings)
configure led's IOMUX and set it off at boot
Signed-off-by: Eric Bénard <eric@xxxxxxxxxx>
---
board/eukrea_cpuimx35/eukrea_cpuimx35.c | 4 ++
board/eukrea_cpuimx35/flash_header.c | 24 ++---------
board/eukrea_cpuimx35/lowlevel.c | 67 ++++--------------------------
3 files changed, 17 insertions(+), 78 deletions(-)
diff --git a/board/eukrea_cpuimx35/eukrea_cpuimx35.c b/board/eukrea_cpuimx35/eukrea_cpuimx35.c
index f358f51..06e5448 100644
--- a/board/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/board/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -210,6 +210,7 @@ static struct pad_desc eukrea_cpuimx35_pads[] = {
MX35_PAD_CONTRAST__GPIO1_1,
MX35_PAD_D3_CLS__GPIO1_4,
+ MX35_PAD_LD23__GPIO3_29,
};
@@ -218,6 +219,9 @@ static int eukrea_cpuimx35_console_init(void)
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
ARRAY_SIZE(eukrea_cpuimx35_pads));
+ /* led default off */
+ gpio_direction_output(32 * 2 + 29, 1);
+
register_device(&eukrea_cpuimx35_serial_device);
return 0;
diff --git a/board/eukrea_cpuimx35/flash_header.c b/board/eukrea_cpuimx35/flash_header.c
index a0ccf5c..05104d4 100644
--- a/board/eukrea_cpuimx35/flash_header.c
+++ b/board/eukrea_cpuimx35/flash_header.c
@@ -9,37 +9,21 @@ void __naked __flash_header_start go(void)
}
struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = {
+ { .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
+ { .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, },
- { .ptr_type = 1, .addr = 0x80000400, .val = 0x12345678, },
+ { .ptr_type = 1, .addr = 0x80000400, .val = 0xda, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, },
{ .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, },
{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
- { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82220080, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x82228080, },
- { .ptr_type = 4, .addr = 0xB8001020, .val = 0x80000028, },
- { .ptr_type = 4, .addr = 0xB8001024, .val = 0x80000028, },
- { .ptr_type = 4, .addr = 0xB8001028, .val = 0x80000028, },
- { .ptr_type = 4, .addr = 0xB800102c, .val = 0x80000028, },
- { .ptr_type = 4, .addr = 0xB8001030, .val = 0x80000028, },
+ { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
};
#define APP_DEST 0x80000000
diff --git a/board/eukrea_cpuimx35/lowlevel.c b/board/eukrea_cpuimx35/lowlevel.c
index 44f3cf0..275bfb2 100644
--- a/board/eukrea_cpuimx35/lowlevel.c
+++ b/board/eukrea_cpuimx35/lowlevel.c
@@ -62,7 +62,6 @@ void __bare_init __naked board_init_lowlevel(void)
{
uint32_t r, s;
unsigned long ccm_base = IMX_CCM_BASE;
- unsigned long iomuxc_base = IMX_IOMUXC_BASE;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
@@ -132,68 +131,20 @@ void __bare_init __naked board_init_lowlevel(void)
if (r > 0x80000000 && r < 0x90000000)
board_init_lowlevel_return();
- /* Set DDR Type to SDRAM, drive strength workaround *
- * 0x00000000 MDDR *
- * 0x00000800 3,3V SDRAM */
-
- r = 0x00000800;
- writel(r, iomuxc_base + 0x794);
- writel(r, iomuxc_base + 0x798);
- writel(r, iomuxc_base + 0x79c);
- writel(r, iomuxc_base + 0x7a0);
- writel(r, iomuxc_base + 0x7a4);
-
- /* MDDR init, enable mDDR*/
- writel(0x00000304, ESDMISC); /* was 0x00000004 */
-
- /* set timing paramters */
- writel(0x00255417, ESDCFG0);
- /* select Precharge-All mode */
+ /* Init Mobile DDR */
+ writel(0x00000004, ESDMISC);
+ writel(0x0000000C, ESDMISC);
+ writel(0x00295729, ESDCFG0);
writel(0x92220000, ESDCTL0);
- /* Precharge-All */
- writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
-
- /* select Load-Mode-Register mode */
- writel(0xB8001000, ESDCTL0);
- /* Load reg EMR2 */
- writeb(0xda, 0x84000000);
- /* Load reg EMR3 */
- writeb(0xda, 0x86000000);
- /* Load reg EMR1 -- enable DLL */
- writeb(0xda, 0x82000400);
- /* Load reg MR -- reset DLL */
- writeb(0xda, 0x80000333);
-
- /* select Precharge-All mode */
- writel(0x92220000, ESDCTL0);
- /* Precharge-All */
- writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
-
- /* select Manual-Refresh mode */
+ writeb(0xda, IMX_SDRAM_CS0 + 0x400);
writel(0xA2220000, ESDCTL0);
- /* Manual-Refresh 2 times */
writel(0x87654321, IMX_SDRAM_CS0);
writel(0x87654321, IMX_SDRAM_CS0);
-
- /* select Load-Mode-Register mode */
writel(0xB2220000, ESDCTL0);
- /* Load reg MR -- CL3, BL8, end DLL reset */
- writeb(0xda, 0x80000233);
- /* Load reg EMR1 -- OCD default */
- writeb(0xda, 0x82000780);
- /* Load reg EMR1 -- OCD exit */
- writeb(0xda, 0x82000400);
-
- /* select normal-operation mode
- * DSIZ32-bit, BL8, COL10-bit, ROW13-bit
- * disable PWT & PRCT
- * disable Auto-Refresh */
- writel(0x82220080, ESDCTL0);
-
- /* enable Auto-Refresh */
- writel(0x82228080, ESDCTL0);
- /* enable Auto-Refresh */
- writel(0x00002000, ESDCTL1);
+ writeb(0xda, IMX_SDRAM_CS0 + 0x33);
+ writeb(0xda, IMX_SDRAM_CS0 + 0x2000000);
+ writel(0x82224080, ESDCTL0);
+ writel(0x00000004, ESDMISC);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
--
1.6.3.3
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