After determining the minimum value for the High period (TCKH) the
remainder of the internal clock pulses is set as the Low period (TCKL).
This causes the i2c clock duty cycle to be much less than 50%.
The fix suggested here, start with TCKH and TCKL at 50% of the internal
clock pulses and adjusts the TCKH and TCKL values from there if the
minimum value for TCKL is not met. This will make sure the i2c clock
duty cycle is at 50% or close 50% whenever possible.
Fixes: 27bce457d588 (i2c: img-scb: Add Imagination Technologies I2C SCB driver)
Signed-off-by: Sifan Naeem <sifan.naeem@xxxxxxxxxx>
Cc: <stable@xxxxxxxxxxxxxxx>
---
drivers/i2c/busses/i2c-img-scb.c | 37 +++++++++++++++++++++----------------
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/i2c/busses/i2c-img-scb.c b/drivers/i2c/busses/i2c-img-scb.c
index 42114a8..fa643d7 100644
--- a/drivers/i2c/busses/i2c-img-scb.c
+++ b/drivers/i2c/busses/i2c-img-scb.c
@@ -1182,27 +1182,32 @@ static int img_i2c_init(struct img_i2c *i2c)
((bitrate_khz * clk_period) / 2))
int_bitrate++;
- /* Setup TCKH value */
- tckh = timing.tckh / clk_period;
- if (timing.tckh % clk_period)
- tckh++;
+ /*
+ * Setup clock duty cycle, start with 50% and adjust TCKH and TCKL
+ * values from there if they don't meet minimum timing requirements
+ */
+ tckh = tckl = int_bitrate / 2;
+ if (int_bitrate % 2)
+ tckl++;
+
+ /* Adjust TCKH and TCKL values */
+ data = timing.tckl / clk_period;
+ if (timing.tckl % clk_period)
+ data++;
+
+ if (tckl < data) {
+ tckl = data;
+ tckh = int_bitrate - tckl;
+ }
if (tckh > 0)
- data = tckh - 1;
- else
- data = 0;
-
- img_i2c_writel(i2c, SCB_TIME_TCKH_REG, data);
-
- /* Setup TCKL value */
- tckl = int_bitrate - tckh;
+ tckh -= 1;
if (tckl > 0)
- data = tckl - 1;
- else
- data = 0;
+ tckl -= 1;
- img_i2c_writel(i2c, SCB_TIME_TCKL_REG, data);
+ img_i2c_writel(i2c, SCB_TIME_TCKH_REG, tckh);
+ img_i2c_writel(i2c, SCB_TIME_TCKL_REG, tckl);
/* Setup TSDH value */
tsdh = timing.tsdh / clk_period;
--
1.7.9.5
--
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