The code to read from the master read fifo, and write to the master
write fifo, checks a bit in an SCB register before every byte to
ensure that the fifo is not full (write fifo) or empty (read fifo).
Due to clock domain crossing inside the SCB block the updated value
of this bit is only visible after 2 cycles.
The scb_wr_rd_fence() function does 2 dummy writes (to the read-only
revision register), and it's called before reading from or writing to the
fifos to ensure that subsequent reads of the fifo status bits do not read
stale values.
The 2 dummy writes are required in all versions of the ip since 2.2.1
Fixes: 27bce457d588 (i2c: img-scb: Add Imagination Technologies I2C SCB driver)
Signed-off-by: Sifan Naeem <sifan.naeem@xxxxxxxxxx>
Cc: <stable@xxxxxxxxxxxxxxx>
---
drivers/i2c/busses/i2c-img-scb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-img-scb.c b/drivers/i2c/busses/i2c-img-scb.c
index 00ffd66..3c1dcd2 100644
--- a/drivers/i2c/busses/i2c-img-scb.c
+++ b/drivers/i2c/busses/i2c-img-scb.c
@@ -1120,7 +1120,7 @@ static int img_i2c_init(struct img_i2c *i2c)
return -EINVAL;
}
- if (rev == REL_SOC_IP_SCB_2_2_1) {
+ if (rev >= REL_SOC_IP_SCB_2_2_1) {
i2c->need_wr_rd_fence = true;
dev_info(i2c->adap.dev.parent, "fence quirk enabled");
}
--
1.7.9.5
--
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