This is a note to let you know that I've just added the patch titled
clk: at91: pll: fix input range validity check
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-at91-pll-fix-input-range-validity-check.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 6c7b03e1aef2e92176435f4fa562cc483422d20f Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@xxxxxxxxxxxxxxxxxx>
Date: Fri, 27 Mar 2015 23:53:15 +0100
Subject: clk: at91: pll: fix input range validity check
From: Boris Brezillon <boris.brezillon@xxxxxxxxxxxxxxxxxx>
commit 6c7b03e1aef2e92176435f4fa562cc483422d20f upstream.
The PLL impose a certain input range to work correctly, but it appears that
this input range does not apply on the input clock (or parent clock) but
on the input clock after it has passed the PLL divisor.
Fix the implementation accordingly.
Signed-off-by: Boris Brezillon <boris.brezillon@xxxxxxxxxxxxxxxxxx>
Reported-by: Jonas Andersson <jonas@xxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/clk/at91/clk-pll.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -173,8 +173,7 @@ static long clk_pll_get_best_div_mul(str
int i = 0;
/* Check if parent_rate is a valid input rate */
- if (parent_rate < characteristics->input.min ||
- parent_rate > characteristics->input.max)
+ if (parent_rate < characteristics->input.min)
return -ERANGE;
/*
@@ -187,6 +186,15 @@ static long clk_pll_get_best_div_mul(str
if (!mindiv)
mindiv = 1;
+ if (parent_rate > characteristics->input.max) {
+ tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
+ if (tmpdiv > PLL_DIV_MAX)
+ return -ERANGE;
+
+ if (tmpdiv > mindiv)
+ mindiv = tmpdiv;
+ }
+
/*
* Calculate the maximum divider which is limited by PLL register
* layout (limited by the MUL or DIV field size).
Patches currently in stable-queue which might be from boris.brezillon@xxxxxxxxxxxxxxxxxx are
queue-4.0/clk-at91-fix-h32mx-prototype-inclusion-in-pmc-header.patch
queue-4.0/clk-at91-pll-fix-input-range-validity-check.patch
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