qOn 16 June 2015 at 13:56, Sasha Levin <sasha.levin@xxxxxxxxxx> wrote: > From: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> > > Two files that get included when building the multi_v7_defconfig target > fail to build when selecting THUMB2_KERNEL for this configuration. > There is a discussion taking place in another thread http://thread.gmane.org/gmane.linux.kernel.stable/137646 about whether fixing the Thumb-2 build for multi_v7_defconfig is appropriate for the -stable trees, since it is unclear if this config ever worked in Thumb2 mode at any point. Since this patch affects PJ4 CPUs, and MVEBU was included in multi_v7_defconfig from the beginning, I don't think multi_v7_defconfig was ever buildable before in Thumb-2 mode Perhaps Arnd could confirm? -- Ard. > In both cases, we can just build the file as ARM code, as none of its > symbols are exported to modules, so there are no interworking concerns. > In the iwmmxt.S case, add ENDPROC() declarations so the symbols are > annotated as functions, resulting in the linker to emit the appropriate > mode switches. > > Acked-by: Nicolas Pitre <nico@xxxxxxxxxx> > Tested-by: Olof Johansson <olof@xxxxxxxxx> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> > Signed-off-by: Russell King <rmk+kernel@xxxxxxxxxxxxxxxx> > (cherry picked from commit 13d1b9575ac2c2da143cd2236b6cf0fc314570f8) > Cc: <stable@xxxxxxxxxxxxxxx> # v3.18+ > Signed-off-by: Kevin Hilman <khilman@xxxxxxxxxx> > Signed-off-by: Sasha Levin <sasha.levin@xxxxxxxxxx> > --- > arch/arm/kernel/Makefile | 1 + > arch/arm/kernel/iwmmxt.S | 13 +++++++++++++ > 2 files changed, 14 insertions(+) > > diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile > index 03120e6..2ecc7d1 100644 > --- a/arch/arm/kernel/Makefile > +++ b/arch/arm/kernel/Makefile > @@ -84,6 +84,7 @@ obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o > obj-$(CONFIG_IWMMXT) += iwmmxt.o > obj-$(CONFIG_PERF_EVENTS) += perf_regs.o > obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o > +CFLAGS_pj4-cp0.o := -marm > AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt > obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o > > diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S > index ad58e56..49fadbd 100644 > --- a/arch/arm/kernel/iwmmxt.S > +++ b/arch/arm/kernel/iwmmxt.S > @@ -58,6 +58,7 @@ > #define MMX_SIZE (0x98) > > .text > + .arm > > /* > * Lazy switching of Concan coprocessor context > @@ -182,6 +183,8 @@ concan_load: > tmcr wCon, r2 > ret lr > > +ENDPROC(iwmmxt_task_enable) > + > /* > * Back up Concan regs to save area and disable access to them > * (mainly for gdb or sleep mode usage) > @@ -232,6 +235,8 @@ ENTRY(iwmmxt_task_disable) > 1: msr cpsr_c, ip @ restore interrupt mode > ldmfd sp!, {r4, pc} > > +ENDPROC(iwmmxt_task_disable) > + > /* > * Copy Concan state to given memory address > * > @@ -268,6 +273,8 @@ ENTRY(iwmmxt_task_copy) > msr cpsr_c, ip @ restore interrupt mode > ret r3 > > +ENDPROC(iwmmxt_task_copy) > + > /* > * Restore Concan state from given memory address > * > @@ -304,6 +311,8 @@ ENTRY(iwmmxt_task_restore) > msr cpsr_c, ip @ restore interrupt mode > ret r3 > > +ENDPROC(iwmmxt_task_restore) > + > /* > * Concan handling on task switch > * > @@ -335,6 +344,8 @@ ENTRY(iwmmxt_task_switch) > mrc p15, 0, r1, c2, c0, 0 > sub pc, lr, r1, lsr #32 @ cpwait and return > > +ENDPROC(iwmmxt_task_switch) > + > /* > * Remove Concan ownership of given task > * > @@ -353,6 +364,8 @@ ENTRY(iwmmxt_task_release) > msr cpsr_c, r2 @ restore interrupts > ret lr > > +ENDPROC(iwmmxt_task_release) > + > .data > concan_owner: > .word 0 > -- > 2.1.0 > -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html