Greg Kroah-Hartman wrote...
> From: Gregory CLEMENT <gregory.clement@xxxxxxxxxxxxxxxxxx>
>
> commit 61819549f572edd7fce53f228c0d8420cdc85f71 upstream.
>
> Level IRQ handlers and edge IRQ handler are managed by tow different
> sets of registers. But currently the driver uses the same mask for the
> both registers. It lead to issues with the following scenario:
(...)
This results in a build breakage:
(...)
| CC drivers/gpio/gpio-mvebu.o
| drivers/gpio/gpio-mvebu.c: In function 'mvebu_gpio_edge_irq_mask':
| drivers/gpio/gpio-mvebu.c:311:4: error: 'struct irq_chip_type' has no member named 'mask_cache_priv'
| drivers/gpio/gpio-mvebu.c:313:2: error: 'struct irq_chip_type' has no member named 'mask_cache_priv'
| drivers/gpio/gpio-mvebu.c: In function 'mvebu_gpio_edge_irq_unmask':
| drivers/gpio/gpio-mvebu.c:326:4: error: 'struct irq_chip_type' has no member named 'mask_cache_priv'
| drivers/gpio/gpio-mvebu.c:327:2: error: 'struct irq_chip_type' has no member named 'mask_cache_priv'
| drivers/gpio/gpio-mvebu.c: In function 'mvebu_gpio_level_irq_mask':
| drivers/gpio/gpio-mvebu.c:340:4: error: 'struct irq_chip_type' has no member named 'mask_cache_priv'
| drivers/gpio/gpio-mvebu.c:341:2: error: 'struct irq_chip_type' has no member named 'mask_cache_priv'
| drivers/gpio/gpio-mvebu.c: In function 'mvebu_gpio_level_irq_unmask':
| drivers/gpio/gpio-mvebu.c:354:4: error: 'struct irq_chip_type' has no member named 'mask_cache_priv'
| drivers/gpio/gpio-mvebu.c:355:2: error: 'struct irq_chip_type' has no member named 'mask_cache_priv'
Perhaps picking
| commit 899f0e66fff36ebb6dd6a83af9aa631f6cb7e0dc
| Author: Gerlando Falauto <gerlando.falauto@xxxxxxxxxxx>
| Date: Mon May 6 14:30:19 2013 +0000
|
| genirq: Generic chip: Add support for per chip type mask cache
will fix this but I couldn't check yet: My box is still busy test-building the
3.14 series.
Christoph
Attachment:
signature.asc
Description: Digital signature