On 3/6/2025 11:43 AM, Paolo Abeni wrote:
> On 3/4/25 5:06 PM, Andrei Botila wrote:
>> diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
>> index 34231b5b9175..709d6c9f7cba 100644
>> --- a/drivers/net/phy/nxp-c45-tja11xx.c
>> +++ b/drivers/net/phy/nxp-c45-tja11xx.c
>> @@ -22,6 +22,11 @@
>> #define PHY_ID_TJA_1103 0x001BB010
>> #define PHY_ID_TJA_1120 0x001BB031
>>
>> +#define VEND1_DEVICE_ID3 0x0004
>> +#define TJA1120_DEV_ID3_SILICON_VERSION GENMASK(15, 12)
>> +#define TJA1120_DEV_ID3_SAMPLE_TYPE GENMASK(11, 8)
>> +#define DEVICE_ID3_SAMPLE_TYPE_R 0x9
>> +
>> #define VEND1_DEVICE_CONTROL 0x0040
>> #define DEVICE_CONTROL_RESET BIT(15)
>> #define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14)
>> @@ -1593,6 +1598,50 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev)
>> return 0;
>> }
>>
>> +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */
>> +static void nxp_c45_tja1120_errata(struct phy_device *phydev)
>> +{
>> + int silicon_version, sample_type;
>> + bool macsec_ability;
>> + int phy_abilities;
>> + int ret = 0;
>> +
>> + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3);
>> + if (ret < 0)
>> + return;
>> +
>> + sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret);
>> + if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R)
>> + return;
>> +
>> + silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret);
>> +
>> + phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
>> + VEND1_PORT_ABILITIES);
>> + macsec_ability = !!(phy_abilities & MACSEC_ABILITY);
>> + if ((!macsec_ability && silicon_version == 2) ||
>> + (macsec_ability && silicon_version == 1)) {
>> + /* TJA1120/TJA1121 PHY configuration errata workaround.
>> + * Apply PHY writes sequence before link up.
>> + */
>> + if (!macsec_ability) {
>> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95);
>> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd);
>> + } else {
>> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7);
>> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893);
>> + }
>> +
>> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0);
>> +
>> + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a);
>> + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1);
>> +
>> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);
>> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);
>
> Please add macro with meaningful names for all the magic numbers used
> above, thanks!
>
> Paolo
>
Hello, these registers are not documented in the datasheet or errata sheet.
The access sequence comes 1-to-1 from the errata so I couldn't use macros.
Regards, Andrei B.
