On Wed, Jan 15, 2025 at 4:33 PM Stefan Eichenberger <eichest@xxxxxxxxx> wrote:
>
> Hi Shengjiu Wang,
>
> On Tue, Jan 14, 2025 at 12:58:24PM +0100, Stefan Eichenberger wrote:
> > Hi Shengjiu Wang,
> >
> > On Tue, Jan 14, 2025 at 03:49:10PM +0800, Shengjiu Wang wrote:
> > > On Mon, Jan 13, 2025 at 5:54 PM Stefan Eichenberger <eichest@xxxxxxxxx> wrote:
> > > >
> > > > From: Stefan Eichenberger <stefan.eichenberger@xxxxxxxxxxx>
> > > >
> > > > Currently, the flags for the ACM clocks are set to 0. This configuration
> > > > causes the fsl-sai audio driver to fail when attempting to set the
> > > > sysclk, returning an EINVAL error. The following error messages
> > > > highlight the issue:
> > > > fsl-sai 59090000.sai: ASoC: error at snd_soc_dai_set_sysclk on 59090000.sai: -22
> > > > imx-hdmi sound-hdmi: failed to set cpu sysclk: -22
> > >
> > > The reason for this error is that the current clock parent can't
> > > support the rate
> > > you require (I think you want 11289600).
> > >
> > > We can configure the dts to provide such source, for example:
> > >
> > > &sai5 {
> > > + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
> > > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
> > > + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
> > > + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
> > > + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
> > > + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
> > > + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
> > > + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
> > > + <&sai5_lpcg 0>;
> > > + assigned-clock-parents = <&aud_pll_div0_lpcg 0>, <&aud_rec1_lpcg 0>;
> > > + assigned-clock-rates = <0>, <0>, <786432000>, <49152000>, <12288000>,
> > > + <722534400>, <45158400>, <11289600>,
> > > + <49152000>;
> > > status = "okay";
> > > };
> > >
> > > Then your case should work.
> > >
> > > >
> > > > By setting the flag CLK_SET_RATE_NO_REPARENT, we signal that the ACM
> > >
> > > I don't think CLK_SET_RATE_NO_REPARENT is a good choice. which will cause
> > > the driver don't get an error from clk_set_rate().
> >
> > Thanks for the proposal, I will try it out tomorrow. Isn't this a
> > problem if other SAIs use the same clock source but with different
> > rates?
> >
> > If we have to define fixed rates in the DTS or else the clock driver
> > will return an error, isn't that a problem? Maybe I should change the
> > sai driver so that it ignores the failure and just takes the rate
> > configured? In the end audio works, even if it can't set the requested
> > rate.
>
> The following clock tree change would allow the driver to work
> in our scenario:
> &sai5 {
> assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
> <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>;
> assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
> assigned-clock-rates = <0>, <11289600>;
> };
In which we configure PLL_0 for 48KHz series (8kHz/16kHz/32kHz/48kHz),
PLL_1 for 44kHz series (11kHz/22kHz/44kHz),
which should fit for most audio requirements.
>
> However, this means we have to switch the parent clock to the audio pll
> 1. For the simple setup with two SAIs, one for analog audio and one for
> HDMI this wouldn't be a problem. But I'm not sure if this is a good
> solution if a customer would add a third SAI which requires again a
> different parent clock rate.
We won't change the PLL's rate in the driver, so as PLL_0 for 48kHz,
PLL_1 for 44kHz, even with a third SAI or more, they should work.
>
> One potential solution could be that the SAI driver tries to first
> derive the clock from the current parent and only if this fails it tries
> to modify its parent clock. What do you think about this solution?
>
It's better to avoid modifying parent rate, as drivers don't know if the parent
is used by another instance.
Best regards
Shengjiu Wang
