On Fri, Jan 10, 2025 at 11:10 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> The PFC_MASK value for the PFC_mx register was previously hardcoded as
> `0x07`, which is correct for SoCs in the RZ/G2L family but insufficient
> for RZ/V2H and RZ/G3E, where the mask value should be `0x0f`. This
> discrepancy caused incorrect PFC register configurations on RZ/V2H and
> RZ/G3E SoCs.
>
> On the RZ/G2L, the PFC_mx bitfields are also 4 bits wide, with bit 4
> marked as reserved. The reserved bits are documented to read as zero and
> be ignored when written. Updating the PFC_MASK definition from `0x07` to
> `0x0f` ensures compatibility with both SoC families while maintaining
> correct behavior on RZ/G2L.
>
> Fixes: 9bd95ac86e70 ("pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC")
> Cc: stable@xxxxxxxxxxxxxxx
> Reported-by: Hien Huynh <hien.huynh.px@xxxxxxxxxxx>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v1->v2
> - Dropped SoC specific configuration
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-pinctrl for v6.14, as it is a fix.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
