On Thu, 19 Dec 2024 10:12:58 +0100, Bence Csókás wrote: > The QSPI peripheral control and status registers are > accessible via the SoC's APB bus, whereas MMIO transactions' > data travels on the AHB bus. > > Microchip documentation and even sample code from Atmel > emphasises the need for a memory barrier before the first > MMIO transaction to the AHB-connected QSPI, and before the > last write to its registers via APB. This is achieved by > the following lines in `atmel_qspi_transfer()`: > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/1] spi: atmel-qspi: Memory barriers after memory-mapped I/O commit: be92ab2de0ee1a13291c3b47b2d7eb24d80c0a2c All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
