On 27. 12. 24, 8:50, Greg KH wrote:
On Fri, Dec 27, 2024 at 02:37:00AM -0500, Alex Deucher wrote:
Commit 73dae652dcac ("drm/amdgpu: rework resume handling for display (v2)")
missed a small code change when it was backported resulting in an automatic
backlight control breakage. Fix the backport.
Note that this patch is not in Linus' tree as it is not required there;
the bug was introduced in the backport.
Fixes: 99a02eab8251 ("drm/amdgpu: rework resume handling for display (v2)")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3853
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx # 6.11.x
So the 6.12.y backport is ok? What exact trees is this fix for?
IMO all trees which received 73dae652dcac are broken. All the backports
call "adev->ip_blocks[i].version->funcs->resume()" and not
"amdgpu_ip_block_resume()" (as in upstream). Incl. 6.12.
And there is a bug report for 6.12 here too:
https://bugzilla.suse.com/show_bug.cgi?id=1234782
$ git grep -A8 'stat.*amdgpu_device_ip_resume_phase3'
releases/5.15.174/drm-amdgpu-rework-resume-handling-for-display-v2.patch:+static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev)
releases/5.15.174/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+{
releases/5.15.174/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ int i, r;
releases/5.15.174/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+
releases/5.15.174/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ for (i = 0; i < adev->num_ip_blocks; i++) {
releases/5.15.174/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
releases/5.15.174/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ continue;
releases/5.15.174/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
releases/5.15.174/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ r = adev->ip_blocks[i].version->funcs->resume(adev);
--
releases/6.1.120/drm-amdgpu-rework-resume-handling-for-display-v2.patch:+static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev)
releases/6.1.120/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+{
releases/6.1.120/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ int i, r;
releases/6.1.120/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+
releases/6.1.120/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ for (i = 0; i < adev->num_ip_blocks; i++) {
releases/6.1.120/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
releases/6.1.120/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ continue;
releases/6.1.120/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
releases/6.1.120/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ r = adev->ip_blocks[i].version->funcs->resume(adev);
--
releases/6.12.5/drm-amdgpu-rework-resume-handling-for-display-v2.patch:+static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev)
releases/6.12.5/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+{
releases/6.12.5/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ int i, r;
releases/6.12.5/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+
releases/6.12.5/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ for (i = 0; i < adev->num_ip_blocks; i++) {
releases/6.12.5/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
releases/6.12.5/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ continue;
releases/6.12.5/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
releases/6.12.5/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ r = adev->ip_blocks[i].version->funcs->resume(adev);
--
releases/6.6.66/drm-amdgpu-rework-resume-handling-for-display-v2.patch:+static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev)
releases/6.6.66/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+{
releases/6.6.66/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ int i, r;
releases/6.6.66/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+
releases/6.6.66/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ for (i = 0; i < adev->num_ip_blocks; i++) {
releases/6.6.66/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
releases/6.6.66/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ continue;
releases/6.6.66/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
releases/6.6.66/drm-amdgpu-rework-resume-handling-for-display-v2.patch-+ r = adev->ip_blocks[i].version->funcs->resume(adev);
thanks,
--
js
suse labs
