This is a note to let you know that I've just added the patch titled
mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x flavor
to the 3.19-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mmc-sdhci-pxav3-fix-sdr50-and-ddr50-capabilities-for-the-armada-38x-flavor.patch
and it can be found in the queue-3.19 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From d4b803c559843e3774736e5108cf6331cf75f64c Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT <gregory.clement@xxxxxxxxxxxxxxxxxx>
Date: Thu, 29 Jan 2015 12:36:24 +0100
Subject: mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x flavor
From: Gregory CLEMENT <gregory.clement@xxxxxxxxxxxxxxxxxx>
commit d4b803c559843e3774736e5108cf6331cf75f64c upstream.
According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register. However,
this register was not part of the device tree binding. Even if the
binding can (and will) be extended we still need handling the case
where this register was not available. In this case we use the
SDHCI_QUIRK_MISSING_CAPS quirk remove them from the capabilities.
This commit is based on the work done by Marcin Wojtas<mw@xxxxxxxxxxxx>
Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxxxxxxxxx>
Signed-off-by: Marcin Wojtas <mw@xxxxxxxxxxxx>
Signed-off-by: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/mmc/host/sdhci-pxav3.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -118,6 +118,20 @@ static int mv_conf_mbus_windows(struct p
return 0;
}
+static int armada_38x_quirks(struct sdhci_host *host)
+{
+ host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
+ /*
+ * According to erratum 'FE-2946959' both SDR50 and DDR50
+ * modes require specific clock adjustments in SDIO3
+ * Configuration register, if the adjustment is not done,
+ * remove them from the capabilities.
+ */
+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+ return 0;
+}
+
static void pxav3_reset(struct sdhci_host *host, u8 mask)
{
struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
@@ -319,6 +333,9 @@ static int sdhci_pxav3_probe(struct plat
clk_prepare_enable(pxa->clk_core);
if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
+ ret = armada_38x_quirks(host);
+ if (ret < 0)
+ goto err_clk_get;
ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
if (ret < 0)
goto err_mbus_win;
Patches currently in stable-queue which might be from gregory.clement@xxxxxxxxxxxxxxxxxx are
queue-3.19/mmc-sdhci-pxav3-fix-armada-38x-controller-s-caps-according-to-erratum-err-7878951.patch
queue-3.19/mmc-sdhci-pxav3-fix-sdr50-and-ddr50-capabilities-for-the-armada-38x-flavor.patch
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