5.4-stable review patch. If anyone has any objections, please let me know.
------------------
From: Shengjiu Wang <shengjiu.wang@xxxxxxx>
commit 101b096bc2549618f18bc08ae3a0e364b3c8fff1 upstream.
Remove the _SHIFT for the mask definition.
Fixes: 17f2142bae4b ("ASoC: fsl_micfil: use GENMASK to define register bit fields")
Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx>
Acked-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Link: https://lore.kernel.org/r/1651736047-28809-1-git-send-email-shengjiu.wang@xxxxxxx
Signed-off-by: Mark Brown <broonie@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
sound/soc/fsl/fsl_micfil.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/sound/soc/fsl/fsl_micfil.h
+++ b/sound/soc/fsl/fsl_micfil.h
@@ -75,9 +75,9 @@
#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
-#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24)
-#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16)
-#define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8)
+#define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24)
+#define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16)
+#define MICFIL_VAD0_CTRL1_INITT GENMASK(12, 8)
#define MICFIL_VAD0_CTRL1_ST10 BIT(4)
#define MICFIL_VAD0_CTRL1_ERIE BIT(3)
#define MICFIL_VAD0_CTRL1_IE BIT(2)
@@ -107,7 +107,7 @@
/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
#define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
-#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8)
+#define MICFIL_VAD0_ZCD_ZCDADJ GENMASK(11, 8)
#define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
#define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
#define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
