On 11/19/2024 9:15 PM, Greg KH wrote:
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On Tue, Nov 19, 2024 at 01:49:33PM +0800, Bin Lan wrote:
From: Mikulas Patocka <mpatocka@xxxxxxxxxx>
ARCH_DMA_MINALIGN was defined as 16 - this is too small - it may be
possible that two unrelated 16-byte allocations share a cache line. If
one of these allocations is written using DMA and the other is written
using cached write, the value that was written with DMA may be
corrupted.
This commit changes ARCH_DMA_MINALIGN to be 128 on PA20 and 32 on PA1.1 -
that's the largest possible cache line size.
As different parisc microarchitectures have different cache line size, we
define arch_slab_minalign(), cache_line_size() and
dma_get_cache_alignment() so that the kernel may tune slab cache
parameters dynamically, based on the detected cache line size.
Signed-off-by: Mikulas Patocka <mpatocka@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Helge Deller <deller@xxxxxx>
Signed-off-by: Bin Lan <bin.lan.cn@xxxxxxxxxxxxx>
---
arch/parisc/Kconfig | 1 +
arch/parisc/include/asm/cache.h | 11 ++++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
You seem to have forgotten to add the git id :(
Thank you. I will send v2 patch for review.
Bin Lan
