On 07/11/2024 12:58, Manivannan Sadhasivam via B4 Relay wrote:
From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> In SM8650, UFS PHY GDSCs doesn't support hardware retention. So using RETAIN_FF_ENABLE is wrong. Moreover, without ALWAYS_ON flag, GDSCs will get powered down during suspend, causing the UFS PHY to loose its state. And this will lead to UFS error similar to below during resume: ufshcd-qcom 1d84000.ufs: ufshcd_uic_hibern8_exit: hibern8 exit failed. ret = 5 ufshcd-qcom 1d84000.ufs: __ufshcd_wl_resume: hibern8 exit failed 5 ufs_device_wlun 0:0:0:49488: ufshcd_wl_resume failed: 5 ufs_device_wlun 0:0:0:49488: PM: dpm_run_callback(): scsi_bus_resume+0x0/0x84 returns 5 ufs_device_wlun 0:0:0:49488: PM: failed to resume async: error 5 Cc: stable@xxxxxxxxxxxxxxx # 6.8 Fixes: c58225b7e3d7 ("clk: qcom: add the SM8650 Global Clock Controller driver, part 1") Suggested-by: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> --- drivers/clk/qcom/gcc-sm8650.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c index fd9d6544bdd5..ddc38caf7160 100644 --- a/drivers/clk/qcom/gcc-sm8650.c +++ b/drivers/clk/qcom/gcc-sm8650.c @@ -3480,7 +3480,7 @@ static struct gdsc ufs_phy_gdsc = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = POLL_CFG_GDSCR | ALWAYS_ON, };static struct gdsc ufs_mem_phy_gdsc = {@@ -3489,7 +3489,7 @@ static struct gdsc ufs_mem_phy_gdsc = { .name = "ufs_mem_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = POLL_CFG_GDSCR | ALWAYS_ON, };static struct gdsc usb30_prim_gdsc = {
Tested-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> # on SM8650-HDK Thanks! Neil
