On 10/9/24 00:20, Zhang Rui wrote: > diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c > index 6513c53c9459..d1006531729a 100644 > --- a/arch/x86/kernel/apic/apic.c > +++ b/arch/x86/kernel/apic/apic.c > @@ -441,6 +441,10 @@ static int lapic_timer_shutdown(struct clock_event_device *evt) > v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); > apic_write(APIC_LVTT, v); > apic_write(APIC_TMICT, 0); > + > + if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) > + wrmsrl(MSR_IA32_TSC_DEADLINE, 0); One last thing, and this is a super nit. We presumably have the actual APIC_LVTT value (v) sitting in a register already. Is there any difference logically between a X86_FEATURE_TSC_DEADLINE_TIMER check and an APIC_LVTT check for APIC_LVT_TIMER_TSCDEADLINE? I suspect this will generate more compact code: if (v & APIC_LVT_TIMER_TSCDEADLINE) wrmsrl(MSR_IA32_TSC_DEADLINE, 0); Does it have any downsides? Oh, and how hot is this path? Is this wrmsr() going to matter? I presume it's pretty cheap because it's one of the special architecturally non-serializing WRMSRs.
