On Wed, Oct 9, 2024 at 9:20 AM Zhang Rui <rui.zhang@xxxxxxxxx> wrote:
>
> This 12-year-old bug prevents some modern processors from achieving
> maximum power savings during suspend. For example, Lunar Lake systems
> gets 0% package C-states during suspend to idle and this causes energy
> star compliance tests to fail.
>
> According to Intel SDM, for the local APIC timer,
> 1. "The initial-count register is a read-write register. A write of 0 to
> the initial-count register effectively stops the local APIC timer, in
> both one-shot and periodic mode."
> 2. "In TSC deadline mode, writes to the initial-count register are
> ignored; and current-count register always reads 0. Instead, timer
> behavior is controlled using the IA32_TSC_DEADLINE MSR."
> "In TSC-deadline mode, writing 0 to the IA32_TSC_DEADLINE MSR disarms
> the local-APIC timer."
>
> Stop the TSC Deadline timer in lapic_timer_shutdown() by writing 0 to
> MSR_IA32_TSC_DEADLINE.
>
> Cc: stable@xxxxxxxxxxxxxxx
> Fixes: 279f1461432c ("x86: apic: Use tsc deadline for oneshot when available")
> Signed-off-by: Zhang Rui <rui.zhang@xxxxxxxxx>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>
x86 folks, this is quite nasty, so please make it high-prio.
Alternatively, I can take it through the PM tree.
> ---
> Changes since V1
> - improve changelog
> ---
> arch/x86/kernel/apic/apic.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index 6513c53c9459..d1006531729a 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -441,6 +441,10 @@ static int lapic_timer_shutdown(struct clock_event_device *evt)
> v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
> apic_write(APIC_LVTT, v);
> apic_write(APIC_TMICT, 0);
> +
> + if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
> + wrmsrl(MSR_IA32_TSC_DEADLINE, 0);
> +
> return 0;
> }
>
> --
> 2.34.1
>
>
