On Tue, Sep 24, 2024 at 09:07:19PM +0200, Ferry Toth wrote:
> Op 20-09-2024 om 17:56 schreef Andy Shevchenko:
> > From: Serge Semin <fancer.lancer@xxxxxxxxx>
> >
> > The recently submitted fix-commit revealed a problem in the iDMA 32-bit
> > platform code. Even though the controller supported only a single master
> > the dw_dma_acpi_filter() method hard-coded two master interfaces with IDs
> > 0 and 1. As a result the sanity check implemented in the commit
> > b336268dde75 ("dmaengine: dw: Add peripheral bus width verification")
> > got incorrect interface data width and thus prevented the client drivers
> > from configuring the DMA-channel with the EINVAL error returned. E.g.,
> > the next error was printed for the PXA2xx SPI controller driver trying
> > to configure the requested channels:
> >
> > > [ 164.525604] pxa2xx_spi_pci 0000:00:07.1: DMA slave config failed
> > > [ 164.536105] pxa2xx_spi_pci 0000:00:07.1: failed to get DMA TX descriptor
> > > [ 164.543213] spidev spi-SPT0001:00: SPI transfer failed: -16
> >
> > The problem would have been spotted much earlier if the iDMA 32-bit
> > controller supported more than one master interfaces. But since it
> > supports just a single master and the iDMA 32-bit specific code just
> > ignores the master IDs in the CTLLO preparation method, the issue has
> > been gone unnoticed so far.
> >
> > Fix the problem by specifying the default master ID for both memory
> > and peripheral devices in the driver data. Thus the issue noticed for
> > the iDMA 32-bit controllers will be eliminated and the ACPI-probed
> > DW DMA controllers will be configured with the correct master ID by
> > default.
...
> Tested-by: Ferry Toth <fntoth@xxxxxxxxx> (Intel Edison-Arduino)
Thanks for testing!
Vinod, can this be queued for v6.12-rc3?
--
With Best Regards,
Andy Shevchenko
