Hello Greg,
Am Wed, Oct 02, 2024 at 02:57:29PM +0200 schrieb Greg Kroah-Hartman:
> 6.11-stable review patch. If anyone has any objections, please let me know.
>
> ------------------
>
> From: Alexander Dahl <ada@xxxxxxxxxxx>
>
> [ Upstream commit 329ca3eed4a9a161515a8714be6ba182321385c7 ]
>
> Previously the MR and SCR registers were just set with the supposedly
> required values, from cached register values (cached reg content
> initialized to zero).
>
> All parts fixed here did not consider the current register (cache)
> content, which would make future support of cs_setup, cs_hold, and
> cs_inactive impossible.
>
> Setting SCBR in atmel_qspi_setup() erases a possible DLYBS setting from
> atmel_qspi_set_cs_timing(). The DLYBS setting is applied by ORing over
> the current setting, without resetting the bits first. All writes to MR
> did not consider possible settings of DLYCS and DLYBCT.
>
> Signed-off-by: Alexander Dahl <ada@xxxxxxxxxxx>
> Fixes: f732646d0ccd ("spi: atmel-quadspi: Add support for configuring CS timing")
> Link: https://patch.msgid.link/20240918082744.379610-2-ada@xxxxxxxxxxx
> Signed-off-by: Mark Brown <broonie@xxxxxxxxxx>
> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
> ---
> drivers/spi/atmel-quadspi.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
> index 466c01b31123b..b557ce94da209 100644
> --- a/drivers/spi/atmel-quadspi.c
> +++ b/drivers/spi/atmel-quadspi.c
> @@ -375,9 +375,9 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
> * If the QSPI controller is set in regular SPI mode, set it in
> * Serial Memory Mode (SMM).
> */
> - if (aq->mr != QSPI_MR_SMM) {
> - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
> - aq->mr = QSPI_MR_SMM;
> + if (!(aq->mr & QSPI_MR_SMM)) {
> + aq->mr |= QSPI_MR_SMM;
> + atmel_qspi_write(aq->scr, aq, QSPI_MR);
This is a write to a wrong register, it was already fixed with
<20240926090356.105789-1-ada@xxxxxxxxxxx> [1] which was taken by Mark
into the spi for-next tree. If you take this patch, please also take
the fixup! Sorry for messing this up, that was my fault.
(Note: I'm AFK from tomorrow until October 13th.)
Thanks
Alex
[1] https://lore.kernel.org/linux-spi/20240926090356.105789-1-ada@xxxxxxxxxxx/T/#u
> }
>
> /* Clear pending interrupts */
> @@ -501,7 +501,8 @@ static int atmel_qspi_setup(struct spi_device *spi)
> if (ret < 0)
> return ret;
>
> - aq->scr = QSPI_SCR_SCBR(scbr);
> + aq->scr &= ~QSPI_SCR_SCBR_MASK;
> + aq->scr |= QSPI_SCR_SCBR(scbr);
> atmel_qspi_write(aq->scr, aq, QSPI_SCR);
>
> pm_runtime_mark_last_busy(ctrl->dev.parent);
> @@ -534,6 +535,7 @@ static int atmel_qspi_set_cs_timing(struct spi_device *spi)
> if (ret < 0)
> return ret;
>
> + aq->scr &= ~QSPI_SCR_DLYBS_MASK;
> aq->scr |= QSPI_SCR_DLYBS(cs_setup);
> atmel_qspi_write(aq->scr, aq, QSPI_SCR);
>
> @@ -549,8 +551,8 @@ static void atmel_qspi_init(struct atmel_qspi *aq)
> atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
>
> /* Set the QSPI controller by default in Serial Memory Mode */
> - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
> - aq->mr = QSPI_MR_SMM;
> + aq->mr |= QSPI_MR_SMM;
> + atmel_qspi_write(aq->mr, aq, QSPI_MR);
>
> /* Enable the QSPI controller */
> atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
> --
> 2.43.0
>
>
>
>
