On October 1, 2024 8:27:55 PM GMT+03:00, Sumit Semwal <sumit.semwal@xxxxxxxxxx> wrote: >Hello Greg, > >On Tue, 30 Jul 2024 at 21:25, Greg Kroah-Hartman ><gregkh@xxxxxxxxxxxxxxxxxxx> wrote: >> >> 6.1-stable review patch. If anyone has any objections, please let me know. >> >> ------------------ >> >> From: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> >> >> [ Upstream commit ba865bdcc688932980b8e5ec2154eaa33cd4a981 ] >> >> Change the UFS QMP PHY to use newer style of QMP PHY bindings (single >> resource region, no per-PHY subnodes). > >This patch breaks UFS on RB5 - it got caught on the merge with >android14-6.1-lts. > >Could we please revert it? [Also on 5.15.165+ kernels]. Not just this one. All "UFS newer style is bindings" must be reverted from these kernels. >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> >> Link: https://lore.kernel.org/r/20231205032552.1583336-8-dmitry.baryshkov@xxxxxxxxxx >> Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx> >> Stable-dep-of: 154ed5ea328d ("arm64: dts: qcom: sm8250: add power-domain to UFS PHY") >> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> >> --- >> arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++-------------- >> 1 file changed, 6 insertions(+), 14 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi >> index 3d02adbc0b62f..194fb00051d66 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi >> @@ -2125,7 +2125,7 @@ ufs_mem_hc: ufshc@1d84000 { >> "jedec,ufs-2.0"; >> reg = <0 0x01d84000 0 0x3000>; >> interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; >> - phys = <&ufs_mem_phy_lanes>; >> + phys = <&ufs_mem_phy>; >> phy-names = "ufsphy"; >> lanes-per-direction = <2>; >> #reset-cells = <1>; >> @@ -2169,10 +2169,8 @@ ufs_mem_hc: ufshc@1d84000 { >> >> ufs_mem_phy: phy@1d87000 { >> compatible = "qcom,sm8250-qmp-ufs-phy"; >> - reg = <0 0x01d87000 0 0x1c0>; >> - #address-cells = <2>; >> - #size-cells = <2>; >> - ranges; >> + reg = <0 0x01d87000 0 0x1000>; >> + >> clock-names = "ref", >> "ref_aux"; >> clocks = <&rpmhcc RPMH_CXO_CLK>, >> @@ -2180,16 +2178,10 @@ ufs_mem_phy: phy@1d87000 { >> >> resets = <&ufs_mem_hc 0>; >> reset-names = "ufsphy"; >> - status = "disabled"; >> >> - ufs_mem_phy_lanes: phy@1d87400 { >> - reg = <0 0x01d87400 0 0x16c>, >> - <0 0x01d87600 0 0x200>, >> - <0 0x01d87c00 0 0x200>, >> - <0 0x01d87800 0 0x16c>, >> - <0 0x01d87a00 0 0x200>; >> - #phy-cells = <0>; >> - }; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> }; >> >> ipa_virt: interconnect@1e00000 { >> -- >> 2.43.0 >> >> >> >> > >Best, >Sumit. -- With best wishes Dmitry
